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Re: Branch breakage on IRIX 6.5

To: rth at redhat dot com
Subject: Re: Branch breakage on IRIX 6.5
From: Mark Mitchell <mark at codesourcery dot com>
Date: Mon, 14 May 2001 11:03:40 -0700
Cc: oldham at codesourcery dot com, gcc-bugs at gcc dot gnu dot org, David dot Billinghurst at riotinto dot com, Gavin Romig-Koch <gavin at cygnus dot com>
Organization: CodeSourcery, LLC
References: <20010514092748.E563@redhat.com><20010514095004L.mitchell@codesourcery.com><20010514100306.A738@redhat.com>

>>>>> "Richard" == Richard Henderson <rth@redhat.com> writes:

    Richard> If this is somewhat predictable (e.g. always slot 0 in
    Richard> the register save area) see the Alpha version for
    Richard> inspiration.  Otherwise, see rs6000.md, eh_set_lr_si +
    Richard> splitter, which delays the memory store until after
    Richard> reload, when the stack offset is known.

OK, I see.

This is a little more than I want to tackle right now.

Gavin, as the MIPS maintainer would you like to make a go at this?  It
would be very useful, since otherwise we will have a significant
regression for MIPS in GCC 3.0.

Thanks,

--
Mark Mitchell                   mark@codesourcery.com
CodeSourcery, LLC               http://www.codesourcery.com

References:
- Re: Branch breakage on IRIX 6.5
  - From: Richard Henderson
- Re: Branch breakage on IRIX 6.5
  - From: Mark Mitchell
- Re: Branch breakage on IRIX 6.5
  - From: Richard Henderson

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