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alpha bootstrap failure wrt loop
- To: Jorn Wolfgang Rennecke <amylaar at cygnus dot com>
- Subject: alpha bootstrap failure wrt loop
- From: Richard Henderson <rth at cygnus dot com>
- Date: Fri, 29 Jan 1999 18:04:54 -0800
- Cc: egcs-bugs at cygnus dot com
With sources up to date as of 1730 PST --
The loop at the end of validate_replace_rtx_1 is (still) being
miscompiled on Alpha, leading to a segv while compiling libgcc.a.
The problem appears to be reading from an uninitialized stack slot:
if (fmt[i] == 'e')
f50: 40 00 5e a4 ldq t1,64(sp)
f54: 01 04 4b 40 addq t1,s2,t0
f58: 00 00 41 28 ldbu t1,0(t0)
f5c: 02 00 e2 73 sextb t1,t1
f60: a1 b5 4c 40 cmpeq t1,0x65,t0
f64: 0a 00 20 e4 beq t0,f90 <validate_replace_rtx_1+0x790>
validate_replace_rtx_1 (&XEXP (x, i), from, to, object);
>>> f68: 58 00 7e a4 ldq t2,88(sp)
f6c: 11 04 ce 45 mov s5,a1
f70: 12 04 ad 45 mov s4,a2
f74: 13 04 ef 45 mov fp,a3
f78: 10 14 61 40 addq t2,0x8,a0
f7c: 22 fe 5f d3 bsr ra,808 <validate_replace_rtx_1+0x8>
The value is spilled sometime later in the loop:
for (j = XVECLEN (x, i) - 1; j >= 0; j--)
f98: 08 00 2c a4 ldq t0,8(s3)
f9c: 00 00 41 a0 ldl t1,0(t0)
fa0: 29 31 40 40 subl t1,0x1,s0
fa4: 0e 00 20 e9 blt s0,fe0 <validate_replace_rtx_1+0x7e0>
>>> fa8: 58 00 9e b5 stq s3,88(sp)
fac: 4a 16 21 41 s8addq s0,0x8,s1
I'll continue to poke at things, but for your cross-compiling
convenience I've put preprocessed source in ~rth/recog.i. Or
you can work in /dot/bang/ if you can stand cross-pond latency.
r~