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RE: Bootstrap failing gencodes miscompiled by stage1 compiler
- To: egcs-bugs at cygnus dot com
- Subject: RE: Bootstrap failing gencodes miscompiled by stage1 compiler
- From: Graham <grahams at rcp dot co dot uk>
- Date: Wed, 07 Oct 1998 21:45:17 +0100
- Reply-To: grahams at rcp dot co dot uk
Hi
I've done some investigations into this failure and
have identified it as a problem with sched-insns-after_reload
optimizations.
The problem is a instruction is being reschuled before a
instruction on which it has a dependency.
You can see the incorrect/correct insn sequences if you compile
with and without the -fno-schedule-insn2 respectively.
Here's the corresponding code from rtl.c
========================================
return_rtx = rtx_alloc (tmp_code); /* if we end up with an insn
expression
then we free this space below. */
format_ptr = GET_RTX_FORMAT (GET_CODE (return_rtx));
Here's edited output from rtl.c.greg
====================================
;; Function read_rtx
;; Start of basic block 21, registers live: 6 [bp] 7 [sp] 22 26 36 59
(insn 1678 270 272 (set (reg:HI 1 %dx)
(subreg:HI (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -292)) 0) 0)) 58 {movhi+1} (nil)
(nil))
(insn/i:HI 272 1678 273 (set (mem/s:HI (reg:SI 5 %edi) 22)
(reg:HI 1 %dx)) 58 {movhi+1} (nil)
(expr_list:REG_DEAD (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -292)) 0)
(nil)))
(note/i 273 272 276 "" NOTE_INSN_DELETED)
(note/i 276 273 278 0 NOTE_INSN_BLOCK_END)
(note 278 276 280 0 NOTE_INSN_BLOCK_END)
(insn:HI 280 278 281 (set (reg:SI 0 %eax)
(zero_extend:SI (mem/s:HI (reg:SI 5 %edi) 21))) 86
{zero_extendhisi2} (nil)
(nil))
(note 281 280 283 "" NOTE_INSN_DELETED)
(note 283 281 285 "" NOTE_INSN_DELETED)
(insn:HI 285 283 1681 (set (reg:SI 0 %eax)
(mem/s:SI (plus:SI (mult:SI (reg:SI 0 %eax)
(const_int 4))
(symbol_ref:SI ("rtx_format"))) 5)) 54 {movsi+2}
(insn_list 280 (nil))
(expr_list:REG_DEAD (reg:SI 0 %eax)
(nil)))
(insn 1681 285 1684 (set (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -268)) 0)
(reg:SI 0 %eax)) 54 {movsi+2} (nil)
(nil))
(insn 1684 1681 288 (set (reg:SI 2 %ecx)
(mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int 8)) 0)) 54 {movsi+2} (nil)
(nil))
(insn:QI 288 1684 290 (set (mem:SI (pre_dec:SI (reg:SI 7 %esp)) 0)
(reg:SI 2 %ecx)) 50 {movsi-2} (nil)
(nil))
(call_insn 290 288 292 (set (reg:SI 0 %eax)
(call (mem:QI (symbol_ref:SI ("read_skip_spaces")) 0)
(const_int 4))) 306 {call_value+1} (nil)
(nil)
(nil))
(insn 292 290 295 (set (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -260)) 0)
(reg:SI 0 %eax)) 54 {movsi+2} (insn_list 290 (nil))
(expr_list:REG_DEAD (reg:SI 0 %eax)
(nil)))
(insn:QI 295 292 296 (set (reg:SI 7 %esp)
(plus:SI (reg:SI 7 %esp)
(const_int 4))) 143 {addsi3+1} (nil)
(nil))
(insn:HI 296 295 297 (set (cc0)
(compare (reg:SI 0 %eax)
(const_int 58))) 12 {cmpsi_1} (insn_list 292 (nil))
(nil))
(jump_insn 297 296 299 (set (pc)
(if_then_else (ne (cc0)
(const_int 0))
(label_ref 363)
(pc))) 280 {bleu+1} (nil)
(nil))
;; End of basic block 21
Here's edited output from rtl.c.shed2
=====================================
;; Function read_rtx
;; -- basic block number 21 from 1678 to 297 --
;; ready list initially:
;; 297
;; insn[1678]: priority = 1, ref_count = 3
;; insn[ 272]: priority = 1, ref_count = 2
;; insn[ 280]: priority = 1, ref_count = 3
;; insn[ 285]: priority = 3, ref_count = 3
;; insn[1681]: priority = 3, ref_count = 2
;; insn[1684]: priority = 1, ref_count = 2
;; insn[ 288]: priority = 3, ref_count = 1
;; insn[ 290]: priority = 3, ref_count = 4
;; insn[ 292]: priority = 3, ref_count = 2
;; insn[ 295]: priority = 3, ref_count = 1
;; insn[ 296]: priority = 3, ref_count = 1
;; insn[ 297]: priority = 2147483399, ref_count = 0
;; ready list at T-1: 297 (7fffff07), now 297
;; ready list at T-2: 295 (3) 292 (3), now 295 292
;; ready list at T-3: 292 (3), now 292
;; ready list at T-4: 290 (3), now 290
;; ready list at T-5: 288 (3), now 288
;; ready list at T-6: 1681 (3) 272 (1) 1684 (1), now 1681 1684 272
;; ready list at T-7: 1684 (1) 272 (1) 285 (3), now 285 1684 272
;; ready list at T-8: 1684 (1) 272 (1), now 1684 272
;; insn 272 has a greater potential hazard, now 272 1684
;; ready list at T-9: 1684 (1) 1678 (1), now 1684 1678
;; launching 280 before 1684 with no stalls at T-10
;; ready list at T-10: 1678 (1) 280 (1), now 280 1678
;; ready list at T-11: 1678 (1), now 1678
;; total time = 11
;; new basic block head = 273
;; new basic block end = 297
(note/i 270 265 273 "" NOTE_INSN_LOOP_END)
;; Start of basic block 21, registers live: 6 [bp] 7 [sp] 22 26 36 59
(note/i 273 270 276 "" NOTE_INSN_DELETED)
(note/i 276 273 278 0 NOTE_INSN_BLOCK_END)
(note 278 276 281 0 NOTE_INSN_BLOCK_END)
(note 281 278 283 "" NOTE_INSN_DELETED)
(note 283 281 1678 "" NOTE_INSN_DELETED)
(insn 1678 283 280 (set (reg:HI 1 %dx)
(subreg:HI (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -292)) 0) 0)) 58 {movhi+1} (nil)
(nil))
(insn:HI 280 1678 1684 (set (reg:SI 0 %eax)
(zero_extend:SI (mem/s:HI (reg:SI 5 %edi) 21))) 86
{zero_extendhisi2} (nil)
(nil))
(insn 1684 280 272 (set (reg:SI 2 %ecx)
(mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int 8)) 0)) 54 {movsi+2} (nil)
(nil))
(insn/i:HI 272 1684 285 (set (mem/s:HI (reg:SI 5 %edi) 22)
(reg:HI 1 %dx)) 58 {movhi+1} (insn_list 1678 (nil))
(expr_list:REG_DEAD (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -292)) 0)
(nil)))
(insn:HI 285 272 1681 (set (reg:SI 0 %eax)
(mem/s:SI (plus:SI (mult:SI (reg:SI 0 %eax)
(const_int 4))
(symbol_ref:SI ("rtx_format"))) 5)) 54 {movsi+2}
(insn_list 280 (nil))
(expr_list:REG_DEAD (reg:SI 0 %eax)
(nil)))
(insn 1681 285 288 (set (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -268)) 0)
(reg:SI 0 %eax)) 54 {movsi+2} (insn_list 285 (nil))
(nil))
(insn:QI 288 1681 290 (set (mem:SI (pre_dec:SI (reg:SI 7 %esp)) 0)
(reg:SI 2 %ecx)) 50 {movsi-2} (insn_list:REG_DEP_OUTPUT 1681
(insn_list:REG_DEP_ANTI 1678 (insn_list:REG_DEP_ANTI 272
(insn_list:REG_DEP_ANTI 280 (insn_list:REG_DEP_ANTI 285 (insn_list 1684
(nil)))))))
(nil))
(call_insn 290 288 292 (set (reg:SI 0 %eax)
(call (mem:QI (symbol_ref:SI ("read_skip_spaces")) 0)
(const_int 4))) 306 {call_value+1} (insn_list:REG_DEP_ANTI
280 (insn_list:REG_DEP_ANTI 1684 (insn_list:REG_DEP_ANTI 288
(insn_list:REG_DEP_ANTI 1678 (insn_list:REG_DEP_ANTI 272
(insn_list:REG_DEP_ANTI 285 (insn_list:REG_DEP_ANTI 1681 (nil))))))))
(nil)
(nil))
(insn 292 290 295 (set (mem:SI (plus:SI (reg:SI 6 %ebp)
(const_int -260)) 0)
(reg:SI 0 %eax)) 54 {movsi+2} (insn_list 290 (nil))
(expr_list:REG_DEAD (reg:SI 0 %eax)
(nil)))
(insn:QI 295 292 296 (set (reg:SI 7 %esp)
(plus:SI (reg:SI 7 %esp)
(const_int 4))) 143 {addsi3+1} (insn_list 290 (nil))
(nil))
(insn:HI 296 295 297 (set (cc0)
(compare (reg:SI 0 %eax)
(const_int 58))) 12 {cmpsi_1} (insn_list 290 (insn_list 292
(nil)))
(nil))
(jump_insn/s 297 296 299 (set (pc)
(if_then_else (ne (cc0)
(const_int 0))
(label_ref 363)
(pc))) 280 {bleu+1} (insn_list:REG_DEP_ANTI 295 (insn_list
292 (insn_list 290 (nil))))
(nil))
;; End of basic block 21
The problem it caused by insn 280 being moved before insn 272.
Graham