This is the mail archive of the
mailing list for the GCC project.
Re: egcs-19980803 (pre-1.1) solaris regressions
- To: law at cygnus dot com
- Subject: Re: egcs-19980803 (pre-1.1) solaris regressions
- From: "David S. Miller" <davem at dm dot cobaltmicro dot com>
- Date: Tue, 18 Aug 1998 09:50:37 -0700
- CC: ghazi at caip dot rutgers dot edu, egcs-bugs at cygnus dot com, rth at cygnus dot com, tm at netcom dot com
- References: <email@example.com>
Date: Tue, 18 Aug 1998 10:42:04 -0600
From: Jeffrey A Law <firstname.lastname@example.org>
This is a bug in reorg. I belive it is supposed to handle these
kinds of inconsistencies in the rtl and basic_block_* data
Actually I think it is a combination of bugs, 2 I can see at the
1) As you mention reorg is broken. I walked through the example and
it does not find the basic blocks correctly and does not scan
the necessary instructions to find resource usages while scheduling
a delay instrution. In this case, it does not set the ANNUL bit in
the instruction because of lost information.
2) Secondarily, I found another peculiar property of PIC during reload
on Sparc. When the reload insns are output, a reference to the
PIC register (%l7) is created but I can't for the life of me figure
out where the compiler accounts for this fact in the register
tables in any way shape or form. What gives?
I'm stumped on #2, can anyone provide a clue?
David S. Miller