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Code generation bug on MIPS R4000


Host:     windows NT 4.0 
Target:   mips-wrs-vxworks (same as mips-gnu-elf)
Binutils: 980418
egcs:     egcs-2.91.23 980411

The following file when compiled yields two code generation bugs.
The first comes from the first argument 'm_upper'. The upper 32-bits
of this argument should be masked off before it is shifted into v0 on line
14. (Actually, I'm not 100% sure about this. The User's Manual for the
chips states that the operand to 'sll' should be a valid sign-extended
32-bit value, which I suppose m_upper should be.)
The second problem shows up on line 18 and 22 below: the return value
(which is in 'v0') is being truncated to the lower 32 bits only, when
it should be all 64 bits.

---t.c---
unsigned long long E(unsigned int m_upper, unsigned short s1, unsigned short s2)
{
    unsigned long long pcr;
    pcr = (m_upper << 22) | (s2 << 16) | (s1);
    return pcr;
}
---end t.c---

$ cc1 -quiet -version -mfp64 -mgp64 -mips3 -mrnames -O3 t.c
GNU C version egcs-2.91.23 980411 (gcc2 ss-980401 experimental) (mips-wrs-vxworks) compiled by GNU C version 2.7-B19.

1         .file   1 "t.c"
2 gcc2_compiled.:
3 __gnu_compiled_c:
4         .text
5         .align  2
6         .globl  E
7         .text
8         .ent    E
9 E:
10        .frame  $sp,0,$ra               # vars= 0, regs= 0/0, args= 0, extra= 0
11        .mask   0x00000000,0
12        .fmask  0x00000000,0
13        andi    $a1,$a1,0xffff
14        sll     $v0,$a0,22
15        sll     $a2,$a2,16
16        or      $v0,$v0,$a2
17        or      $v0,$v0,$a1
18        dsll    $v0,$v0,32
19        .set    noreorder
20        .set    nomacro
21        j       $31
22        dsrl    $v0,$v0,32
23        .set    macro
24        .set    reorder
25
26        .end    E



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