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Re: egcs-2.91.24 19980418 : internal error--unrecognizable insn (ultrasparc)
- To: Laurent Bonnaud <bonnaud at irisa dot fr>, jfc at mit dot edu, rth at cygnus dot com
- Subject: Re: egcs-2.91.24 19980418 : internal error--unrecognizable insn (ultrasparc)
- From: Jim Wilson <wilson at cygnus dot com>
- Date: Mon, 27 Apr 1998 22:32:54 -0700
- cc: egcs-bugs at cygnus dot com
host=target=sparc-sun-solaris2.5.1
This is the info I needed. Configured for the right target, I could easily
reproduce the problem.
This is a bug with the recent sparc.md changes from John Carr. I think this
patch fixes the problem.
Mon Apr 27 22:23:52 1998 Jim Wilson <wilson@cygnus.com>
* sparc.md (mulsidi3): Call const v8plus and v8plus routines.
(mulsidi3_v8plus, const_mulsidi3_v8plus): Delete asterisk from name.
(smuldi3_highpart): Call const v8plus routine.
(smulsi3_highpart_v8plus): Renamed from smulsidi3_highpart_v8plus.
(const_smulsi3_highpart_v8plus): New pattern.
(smulsi3_highpart_sp32): Renamed from smulsidi3_highpart_sp32.
(umulsidi3): Call const v8plus routine.
(umulsi3_highpart): Handle const before v8plus. Call const v8plus
routine.
(umulsi3_highpart_v8plus): Renamed from umulsidi3_highpart_v8plus.
(umulsi3_highpart_sp32): Renamed from umulsidi3_highpart_sp32.
Index: sparc.md
===================================================================
RCS file: /egcs/carton/cvsfiles/egcs/gcc/config/sparc/sparc.md,v
retrieving revision 1.18
diff -p -r1.18 sparc.md
*** sparc.md 1998/04/18 01:24:59 1.18
--- sparc.md 1998/04/28 05:23:33
*************** return \"srl %1,0,%0\";
*** 4049,4062 ****
{
if (CONSTANT_P (operands[2]))
{
emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2]));
DONE;
}
}")
;; V9 puts the 64 bit product in a 64 bit register. Only out or global
;; registers can hold 64 bit values in the V8plus environment.
! (define_insn "*mulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
--- 4049,4073 ----
{
if (CONSTANT_P (operands[2]))
{
+ if (TARGET_V8PLUS)
+ {
+ emit_insn (gen_const_mulsidi3_v8plus (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
emit_insn (gen_const_mulsidi3 (operands[0], operands[1], operands[2]));
DONE;
}
+ if (TARGET_V8PLUS)
+ {
+ emit_insn (gen_mulsidi3_v8plus (operands[0], operands[1], operands[2]));
+ DONE;
+ }
}")
;; V9 puts the 64 bit product in a 64 bit register. Only out or global
;; registers can hold 64 bit values in the V8plus environment.
! (define_insn "mulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
(sign_extend:DI (match_operand:SI 2 "register_operand" "r,r"))))
*************** return \"srl %1,0,%0\";
*** 4067,4073 ****
smul %1,%2,%3\;srlx %3,32,%H0\;mov %3,%L0"
[(set_attr "length" "2,3")])
! (define_insn "*const_mulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
(match_operand:SI 2 "small_int" "I,I")))
--- 4078,4084 ----
smul %1,%2,%3\;srlx %3,32,%H0\;mov %3,%L0"
[(set_attr "length" "2,3")])
! (define_insn "const_mulsidi3_v8plus"
[(set (match_operand:DI 0 "register_operand" "=h,r")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
(match_operand:SI 2 "small_int" "I,I")))
*************** return \"srl %1,0,%0\";
*** 4117,4134 ****
{
if (CONSTANT_P (operands[2]))
{
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
DONE;
}
if (TARGET_V8PLUS)
{
! emit_insn (gen_smulsidi3_highpart_v8plus (operands[0], operands[1],
! operands[2], GEN_INT (32)));
DONE;
}
}")
! (define_insn "smulsidi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
--- 4128,4153 ----
{
if (CONSTANT_P (operands[2]))
{
+ if (TARGET_V8PLUS)
+ {
+ emit_insn (gen_const_smulsi3_highpart_v8plus (operands[0],
+ operands[1],
+ operands[2],
+ GEN_INT (32)));
+ DONE;
+ }
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[1], operands[2]));
DONE;
}
if (TARGET_V8PLUS)
{
! emit_insn (gen_smulsi3_highpart_v8plus (operands[0], operands[1],
! operands[2], GEN_INT (32)));
DONE;
}
}")
! (define_insn "smulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
*************** return \"srl %1,0,%0\";
*** 4141,4147 ****
smul %1,%2,%4\;srlx %4,%3,%0"
[(set_attr "length" "2")])
! (define_insn "*smulsidi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
--- 4160,4179 ----
smul %1,%2,%4\;srlx %4,%3,%0"
[(set_attr "length" "2")])
! (define_insn "const_smulsi3_highpart_v8plus"
! [(set (match_operand:SI 0 "register_operand" "=h,r")
! (truncate:SI
! (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
! (match_operand:SI 2 "register_operand" "r,r"))
! (match_operand:SI 3 "const_int_operand" "i,i"))))
! (clobber (match_scratch:SI 4 "=X,&h"))]
! "TARGET_V8PLUS"
! "@
! smul %1,%2,%0\;srlx %0,%3,%0
! smul %1,%2,%4\;srlx %4,%3,%0"
! [(set_attr "length" "2")])
!
! (define_insn "*smulsi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
*************** return \"srl %1,0,%0\";
*** 4170,4175 ****
--- 4202,4213 ----
{
if (CONSTANT_P (operands[2]))
{
+ if (TARGET_V8PLUS)
+ {
+ emit_insn (gen_const_umulsidi3_v8plus (operands[0], operands[1],
+ operands[2]));
+ DONE;
+ }
emit_insn (gen_const_umulsidi3 (operands[0], operands[1], operands[2]));
DONE;
}
*************** return \"srl %1,0,%0\";
*** 4239,4258 ****
"TARGET_HARD_MUL"
"
{
! if (TARGET_V8PLUS)
{
! emit_insn (gen_umulsidi3_highpart_v8plus (operands[0], operands[1],
! operands[2], GEN_INT (32)));
DONE;
}
! if (CONSTANT_P (operands[2]))
{
! emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
DONE;
}
}")
! (define_insn "umulsidi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
--- 4277,4304 ----
"TARGET_HARD_MUL"
"
{
! if (CONSTANT_P (operands[2]))
{
! if (TARGET_V8PLUS)
! {
! emit_insn (gen_const_umulsi3_highpart_v8plus (operands[0],
! operands[1],
! operands[2],
! GEN_INT (32)));
! DONE;
! }
! emit_insn (gen_const_umulsi3_highpart (operands[0], operands[1], operands[2]));
DONE;
}
! if (TARGET_V8PLUS)
{
! emit_insn (gen_umulsi3_highpart_v8plus (operands[0], operands[1],
! operands[2], GEN_INT (32)));
DONE;
}
}")
! (define_insn "umulsi3_highpart_v8plus"
[(set (match_operand:SI 0 "register_operand" "=h,r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r,r"))
*************** return \"srl %1,0,%0\";
*** 4278,4284 ****
umul %1,%2,%4\;srlx %4,%3,%0"
[(set_attr "length" "2")])
! (define_insn "*umulsidi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
--- 4324,4330 ----
umul %1,%2,%4\;srlx %4,%3,%0"
[(set_attr "length" "2")])
! (define_insn "*umulsi3_highpart_sp32"
[(set (match_operand:SI 0 "register_operand" "=r")
(truncate:SI
(lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))