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77c9c6c2 | 1 | /* Expand the basic unary and binary arithmetic operations, for GNU compiler. |
23a5b65a | 2 | Copyright (C) 1987-2014 Free Software Foundation, Inc. |
77c9c6c2 | 3 | |
1322177d | 4 | This file is part of GCC. |
77c9c6c2 | 5 | |
1322177d LB |
6 | GCC is free software; you can redistribute it and/or modify it under |
7 | the terms of the GNU General Public License as published by the Free | |
9dcd6f09 | 8 | Software Foundation; either version 3, or (at your option) any later |
1322177d | 9 | version. |
77c9c6c2 | 10 | |
1322177d LB |
11 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
12 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
14 | for more details. | |
77c9c6c2 RK |
15 | |
16 | You should have received a copy of the GNU General Public License | |
9dcd6f09 NC |
17 | along with GCC; see the file COPYING3. If not see |
18 | <http://www.gnu.org/licenses/>. */ | |
77c9c6c2 RK |
19 | |
20 | ||
21 | #include "config.h" | |
670ee920 | 22 | #include "system.h" |
4977bab6 ZW |
23 | #include "coretypes.h" |
24 | #include "tm.h" | |
718f9c0f | 25 | #include "diagnostic-core.h" |
dff01034 KG |
26 | |
27 | /* Include insn-config.h before expr.h so that HAVE_conditional_move | |
dc297297 | 28 | is properly defined. */ |
dff01034 | 29 | #include "insn-config.h" |
77c9c6c2 RK |
30 | #include "rtl.h" |
31 | #include "tree.h" | |
d8a2d370 DN |
32 | #include "stor-layout.h" |
33 | #include "stringpool.h" | |
34 | #include "varasm.h" | |
6baf1cc8 | 35 | #include "tm_p.h" |
77c9c6c2 | 36 | #include "flags.h" |
49ad7cfa | 37 | #include "function.h" |
52a11cbf | 38 | #include "except.h" |
77c9c6c2 | 39 | #include "expr.h" |
e78d8e51 ZW |
40 | #include "optabs.h" |
41 | #include "libfuncs.h" | |
77c9c6c2 | 42 | #include "recog.h" |
2829c155 | 43 | #include "reload.h" |
87ff9c8e | 44 | #include "ggc.h" |
4a69cf79 | 45 | #include "basic-block.h" |
c15c90bb | 46 | #include "target.h" |
77c9c6c2 | 47 | |
4bcbfa03 | 48 | struct target_optabs default_target_optabs; |
3e9c326a | 49 | struct target_libfuncs default_target_libfuncs; |
135204dd | 50 | struct target_optabs *this_fn_optabs = &default_target_optabs; |
4bcbfa03 RS |
51 | #if SWITCHABLE_TARGET |
52 | struct target_optabs *this_target_optabs = &default_target_optabs; | |
3e9c326a | 53 | struct target_libfuncs *this_target_libfuncs = &default_target_libfuncs; |
4bcbfa03 | 54 | #endif |
34220a12 | 55 | |
3e9c326a RS |
56 | #define libfunc_hash \ |
57 | (this_target_libfuncs->x_libfunc_hash) | |
19c3fc24 | 58 | |
f90b7a5a PB |
59 | static void prepare_float_lib_cmp (rtx, rtx, enum rtx_code, rtx *, |
60 | enum machine_mode *); | |
9cce5b20 | 61 | static rtx expand_unop_direct (enum machine_mode, optab, rtx, rtx, int); |
b55f62cc | 62 | static void emit_libcall_block_1 (rtx, rtx, rtx, rtx, bool); |
842a431a | 63 | |
8a33f100 JH |
64 | /* Debug facility for use in GDB. */ |
65 | void debug_optab_libfuncs (void); | |
66 | ||
79b87c74 MM |
67 | /* Prefixes for the current version of decimal floating point (BID vs. DPD) */ |
68 | #if ENABLE_DECIMAL_BID_FORMAT | |
69 | #define DECIMAL_PREFIX "bid_" | |
70 | #else | |
71 | #define DECIMAL_PREFIX "dpd_" | |
72 | #endif | |
8a33f100 | 73 | \f |
3e9c326a | 74 | /* Used for libfunc_hash. */ |
8a33f100 JH |
75 | |
76 | static hashval_t | |
77 | hash_libfunc (const void *p) | |
78 | { | |
79 | const struct libfunc_entry *const e = (const struct libfunc_entry *) p; | |
5714c34f | 80 | return ((e->mode1 + e->mode2 * NUM_MACHINE_MODES) ^ e->op); |
8a33f100 JH |
81 | } |
82 | ||
3e9c326a | 83 | /* Used for libfunc_hash. */ |
8a33f100 JH |
84 | |
85 | static int | |
86 | eq_libfunc (const void *p, const void *q) | |
87 | { | |
88 | const struct libfunc_entry *const e1 = (const struct libfunc_entry *) p; | |
89 | const struct libfunc_entry *const e2 = (const struct libfunc_entry *) q; | |
cd1440b1 | 90 | return e1->op == e2->op && e1->mode1 == e2->mode1 && e1->mode2 == e2->mode2; |
8a33f100 JH |
91 | } |
92 | ||
93 | /* Return libfunc corresponding operation defined by OPTAB converting | |
94 | from MODE2 to MODE1. Trigger lazy initialization if needed, return NULL | |
95 | if no libfunc is available. */ | |
96 | rtx | |
97 | convert_optab_libfunc (convert_optab optab, enum machine_mode mode1, | |
98 | enum machine_mode mode2) | |
99 | { | |
100 | struct libfunc_entry e; | |
101 | struct libfunc_entry **slot; | |
102 | ||
cd1440b1 RH |
103 | /* ??? This ought to be an assert, but not all of the places |
104 | that we expand optabs know about the optabs that got moved | |
105 | to being direct. */ | |
106 | if (!(optab >= FIRST_CONV_OPTAB && optab <= LAST_CONVLIB_OPTAB)) | |
107 | return NULL_RTX; | |
108 | ||
109 | e.op = optab; | |
8a33f100 JH |
110 | e.mode1 = mode1; |
111 | e.mode2 = mode2; | |
cd1440b1 RH |
112 | slot = (struct libfunc_entry **) |
113 | htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
8a33f100 JH |
114 | if (!slot) |
115 | { | |
cd1440b1 RH |
116 | const struct convert_optab_libcall_d *d |
117 | = &convlib_def[optab - FIRST_CONV_OPTAB]; | |
118 | ||
119 | if (d->libcall_gen == NULL) | |
120 | return NULL; | |
121 | ||
122 | d->libcall_gen (optab, d->libcall_basename, mode1, mode2); | |
123 | slot = (struct libfunc_entry **) | |
124 | htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
125 | if (!slot) | |
126 | return NULL; | |
8a33f100 JH |
127 | } |
128 | return (*slot)->libfunc; | |
129 | } | |
130 | ||
131 | /* Return libfunc corresponding operation defined by OPTAB in MODE. | |
132 | Trigger lazy initialization if needed, return NULL if no libfunc is | |
133 | available. */ | |
134 | rtx | |
135 | optab_libfunc (optab optab, enum machine_mode mode) | |
136 | { | |
137 | struct libfunc_entry e; | |
138 | struct libfunc_entry **slot; | |
139 | ||
cd1440b1 RH |
140 | /* ??? This ought to be an assert, but not all of the places |
141 | that we expand optabs know about the optabs that got moved | |
142 | to being direct. */ | |
143 | if (!(optab >= FIRST_NORM_OPTAB && optab <= LAST_NORMLIB_OPTAB)) | |
144 | return NULL_RTX; | |
145 | ||
146 | e.op = optab; | |
8a33f100 JH |
147 | e.mode1 = mode; |
148 | e.mode2 = VOIDmode; | |
cd1440b1 RH |
149 | slot = (struct libfunc_entry **) |
150 | htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
8a33f100 JH |
151 | if (!slot) |
152 | { | |
cd1440b1 RH |
153 | const struct optab_libcall_d *d |
154 | = &normlib_def[optab - FIRST_NORM_OPTAB]; | |
155 | ||
156 | if (d->libcall_gen == NULL) | |
157 | return NULL; | |
158 | ||
159 | d->libcall_gen (optab, d->libcall_basename, d->libcall_suffix, mode); | |
160 | slot = (struct libfunc_entry **) | |
161 | htab_find_slot (libfunc_hash, &e, NO_INSERT); | |
162 | if (!slot) | |
163 | return NULL; | |
8a33f100 JH |
164 | } |
165 | return (*slot)->libfunc; | |
166 | } | |
79b87c74 | 167 | |
77c9c6c2 | 168 | \f |
2f937369 | 169 | /* Add a REG_EQUAL note to the last insn in INSNS. TARGET is being set to |
77c9c6c2 RK |
170 | the result of operation CODE applied to OP0 (and OP1 if it is a binary |
171 | operation). | |
172 | ||
173 | If the last insn does not set TARGET, don't do anything, but return 1. | |
174 | ||
853f8f1c SB |
175 | If the last insn or a previous insn sets TARGET and TARGET is one of OP0 |
176 | or OP1, don't add the REG_EQUAL note but return 0. Our caller can then | |
177 | try again, ensuring that TARGET is not one of the operands. */ | |
77c9c6c2 RK |
178 | |
179 | static int | |
0c20a65f | 180 | add_equal_note (rtx insns, rtx target, enum rtx_code code, rtx op0, rtx op1) |
77c9c6c2 | 181 | { |
853f8f1c | 182 | rtx last_insn, set; |
77c9c6c2 RK |
183 | rtx note; |
184 | ||
e3feb571 | 185 | gcc_assert (insns && INSN_P (insns) && NEXT_INSN (insns)); |
2f937369 | 186 | |
ec8e098d PB |
187 | if (GET_RTX_CLASS (code) != RTX_COMM_ARITH |
188 | && GET_RTX_CLASS (code) != RTX_BIN_ARITH | |
189 | && GET_RTX_CLASS (code) != RTX_COMM_COMPARE | |
190 | && GET_RTX_CLASS (code) != RTX_COMPARE | |
191 | && GET_RTX_CLASS (code) != RTX_UNARY) | |
2f937369 DM |
192 | return 1; |
193 | ||
194 | if (GET_CODE (target) == ZERO_EXTRACT) | |
195 | return 1; | |
196 | ||
197 | for (last_insn = insns; | |
198 | NEXT_INSN (last_insn) != NULL_RTX; | |
199 | last_insn = NEXT_INSN (last_insn)) | |
200 | ; | |
201 | ||
6da26889 JJ |
202 | /* If TARGET is in OP0 or OP1, punt. We'd end up with a note referencing |
203 | a value changing in the insn, so the note would be invalid for CSE. */ | |
204 | if (reg_overlap_mentioned_p (target, op0) | |
205 | || (op1 && reg_overlap_mentioned_p (target, op1))) | |
206 | { | |
207 | if (MEM_P (target) | |
208 | && (rtx_equal_p (target, op0) | |
209 | || (op1 && rtx_equal_p (target, op1)))) | |
210 | { | |
211 | /* For MEM target, with MEM = MEM op X, prefer no REG_EQUAL note | |
212 | over expanding it as temp = MEM op X, MEM = temp. If the target | |
213 | supports MEM = MEM op X instructions, it is sometimes too hard | |
214 | to reconstruct that form later, especially if X is also a memory, | |
215 | and due to multiple occurrences of addresses the address might | |
216 | be forced into register unnecessarily. | |
217 | Note that not emitting the REG_EQUIV note might inhibit | |
218 | CSE in some cases. */ | |
219 | set = single_set (last_insn); | |
220 | if (set | |
221 | && GET_CODE (SET_SRC (set)) == code | |
222 | && MEM_P (SET_DEST (set)) | |
223 | && (rtx_equal_p (SET_DEST (set), XEXP (SET_SRC (set), 0)) | |
224 | || (op1 && rtx_equal_p (SET_DEST (set), | |
225 | XEXP (SET_SRC (set), 1))))) | |
226 | return 1; | |
227 | } | |
228 | return 0; | |
229 | } | |
230 | ||
c8912e53 | 231 | set = set_for_reg_notes (last_insn); |
2f937369 DM |
232 | if (set == NULL_RTX) |
233 | return 1; | |
234 | ||
235 | if (! rtx_equal_p (SET_DEST (set), target) | |
f9d36a92 | 236 | /* For a STRICT_LOW_PART, the REG_NOTE applies to what is inside it. */ |
2f937369 | 237 | && (GET_CODE (SET_DEST (set)) != STRICT_LOW_PART |
f9d36a92 | 238 | || ! rtx_equal_p (XEXP (SET_DEST (set), 0), target))) |
77c9c6c2 RK |
239 | return 1; |
240 | ||
ec8e098d | 241 | if (GET_RTX_CLASS (code) == RTX_UNARY) |
e2f00837 JJ |
242 | switch (code) |
243 | { | |
244 | case FFS: | |
245 | case CLZ: | |
246 | case CTZ: | |
247 | case CLRSB: | |
248 | case POPCOUNT: | |
249 | case PARITY: | |
250 | case BSWAP: | |
251 | if (GET_MODE (op0) != VOIDmode && GET_MODE (target) != GET_MODE (op0)) | |
252 | { | |
253 | note = gen_rtx_fmt_e (code, GET_MODE (op0), copy_rtx (op0)); | |
254 | if (GET_MODE_SIZE (GET_MODE (op0)) | |
255 | > GET_MODE_SIZE (GET_MODE (target))) | |
256 | note = simplify_gen_unary (TRUNCATE, GET_MODE (target), | |
257 | note, GET_MODE (op0)); | |
258 | else | |
259 | note = simplify_gen_unary (ZERO_EXTEND, GET_MODE (target), | |
260 | note, GET_MODE (op0)); | |
261 | break; | |
262 | } | |
263 | /* FALLTHRU */ | |
264 | default: | |
265 | note = gen_rtx_fmt_e (code, GET_MODE (target), copy_rtx (op0)); | |
266 | break; | |
267 | } | |
77c9c6c2 | 268 | else |
9e6a5703 | 269 | note = gen_rtx_fmt_ee (code, GET_MODE (target), copy_rtx (op0), copy_rtx (op1)); |
77c9c6c2 | 270 | |
2f937369 | 271 | set_unique_reg_note (last_insn, REG_EQUAL, note); |
77c9c6c2 RK |
272 | |
273 | return 1; | |
274 | } | |
275 | \f | |
a484f6ba AS |
276 | /* Given two input operands, OP0 and OP1, determine what the correct from_mode |
277 | for a widening operation would be. In most cases this would be OP0, but if | |
278 | that's a constant it'll be VOIDmode, which isn't useful. */ | |
279 | ||
280 | static enum machine_mode | |
281 | widened_mode (enum machine_mode to_mode, rtx op0, rtx op1) | |
282 | { | |
283 | enum machine_mode m0 = GET_MODE (op0); | |
284 | enum machine_mode m1 = GET_MODE (op1); | |
285 | enum machine_mode result; | |
286 | ||
287 | if (m0 == VOIDmode && m1 == VOIDmode) | |
288 | return to_mode; | |
289 | else if (m0 == VOIDmode || GET_MODE_SIZE (m0) < GET_MODE_SIZE (m1)) | |
290 | result = m1; | |
291 | else | |
292 | result = m0; | |
293 | ||
294 | if (GET_MODE_SIZE (result) > GET_MODE_SIZE (to_mode)) | |
295 | return to_mode; | |
296 | ||
297 | return result; | |
298 | } | |
299 | \f | |
4df199d1 JH |
300 | /* Like optab_handler, but for widening_operations that have a |
301 | TO_MODE and a FROM_MODE. */ | |
302 | ||
303 | enum insn_code | |
304 | widening_optab_handler (optab op, enum machine_mode to_mode, | |
305 | enum machine_mode from_mode) | |
306 | { | |
307 | unsigned scode = (op << 16) | to_mode; | |
308 | if (to_mode != from_mode && from_mode != VOIDmode) | |
309 | { | |
310 | /* ??? Why does find_widening_optab_handler_and_mode attempt to | |
311 | widen things that can't be widened? E.g. add_optab... */ | |
312 | if (op > LAST_CONV_OPTAB) | |
313 | return CODE_FOR_nothing; | |
314 | scode |= from_mode << 8; | |
315 | } | |
316 | return raw_optab_handler (scode); | |
317 | } | |
318 | ||
5dfe80ba AS |
319 | /* Find a widening optab even if it doesn't widen as much as we want. |
320 | E.g. if from_mode is HImode, and to_mode is DImode, and there is no | |
321 | direct HI->SI insn, then return SI->DI, if that exists. | |
322 | If PERMIT_NON_WIDENING is non-zero then this can be used with | |
323 | non-widening optabs also. */ | |
324 | ||
325 | enum insn_code | |
326 | find_widening_optab_handler_and_mode (optab op, enum machine_mode to_mode, | |
327 | enum machine_mode from_mode, | |
328 | int permit_non_widening, | |
329 | enum machine_mode *found_mode) | |
330 | { | |
331 | for (; (permit_non_widening || from_mode != to_mode) | |
332 | && GET_MODE_SIZE (from_mode) <= GET_MODE_SIZE (to_mode) | |
333 | && from_mode != VOIDmode; | |
334 | from_mode = GET_MODE_WIDER_MODE (from_mode)) | |
335 | { | |
336 | enum insn_code handler = widening_optab_handler (op, to_mode, | |
337 | from_mode); | |
338 | ||
339 | if (handler != CODE_FOR_nothing) | |
340 | { | |
341 | if (found_mode) | |
342 | *found_mode = from_mode; | |
343 | return handler; | |
344 | } | |
345 | } | |
346 | ||
347 | return CODE_FOR_nothing; | |
348 | } | |
349 | \f | |
835532b8 RK |
350 | /* Widen OP to MODE and return the rtx for the widened operand. UNSIGNEDP |
351 | says whether OP is signed or unsigned. NO_EXTEND is nonzero if we need | |
0c20a65f | 352 | not actually do a sign-extend or zero-extend, but can leave the |
835532b8 RK |
353 | higher-order bits of the result rtx undefined, for example, in the case |
354 | of logical operations, but not right shifts. */ | |
355 | ||
356 | static rtx | |
0c20a65f AJ |
357 | widen_operand (rtx op, enum machine_mode mode, enum machine_mode oldmode, |
358 | int unsignedp, int no_extend) | |
835532b8 RK |
359 | { |
360 | rtx result; | |
361 | ||
8041889f RK |
362 | /* If we don't have to extend and this is a constant, return it. */ |
363 | if (no_extend && GET_MODE (op) == VOIDmode) | |
364 | return op; | |
365 | ||
366 | /* If we must extend do so. If OP is a SUBREG for a promoted object, also | |
367 | extend since it will be more efficient to do so unless the signedness of | |
368 | a promoted object differs from our extension. */ | |
835532b8 | 369 | if (! no_extend |
cb8f73be | 370 | || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op) |
362d42dc | 371 | && SUBREG_CHECK_PROMOTED_SIGN (op, unsignedp))) |
0661a3de | 372 | return convert_modes (mode, oldmode, op, unsignedp); |
835532b8 | 373 | |
a78a8cc4 | 374 | /* If MODE is no wider than a single word, we return a lowpart or paradoxical |
835532b8 RK |
375 | SUBREG. */ |
376 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
a78a8cc4 | 377 | return gen_lowpart (mode, force_reg (GET_MODE (op), op)); |
835532b8 RK |
378 | |
379 | /* Otherwise, get an object of MODE, clobber it, and set the low-order | |
380 | part to OP. */ | |
381 | ||
382 | result = gen_reg_rtx (mode); | |
c41c1387 | 383 | emit_clobber (result); |
835532b8 RK |
384 | emit_move_insn (gen_lowpart (GET_MODE (op), result), op); |
385 | return result; | |
386 | } | |
387 | \f | |
71d46ca5 MM |
388 | /* Return the optab used for computing the operation given by the tree code, |
389 | CODE and the tree EXP. This function is not always usable (for example, it | |
390 | cannot give complete results for multiplication or division) but probably | |
391 | ought to be relied on more widely throughout the expander. */ | |
26277d41 | 392 | optab |
71d46ca5 MM |
393 | optab_for_tree_code (enum tree_code code, const_tree type, |
394 | enum optab_subtype subtype) | |
26277d41 PB |
395 | { |
396 | bool trapv; | |
397 | switch (code) | |
398 | { | |
399 | case BIT_AND_EXPR: | |
400 | return and_optab; | |
401 | ||
402 | case BIT_IOR_EXPR: | |
403 | return ior_optab; | |
404 | ||
405 | case BIT_NOT_EXPR: | |
406 | return one_cmpl_optab; | |
407 | ||
408 | case BIT_XOR_EXPR: | |
409 | return xor_optab; | |
410 | ||
98449720 RH |
411 | case MULT_HIGHPART_EXPR: |
412 | return TYPE_UNSIGNED (type) ? umul_highpart_optab : smul_highpart_optab; | |
413 | ||
26277d41 PB |
414 | case TRUNC_MOD_EXPR: |
415 | case CEIL_MOD_EXPR: | |
416 | case FLOOR_MOD_EXPR: | |
417 | case ROUND_MOD_EXPR: | |
418 | return TYPE_UNSIGNED (type) ? umod_optab : smod_optab; | |
419 | ||
420 | case RDIV_EXPR: | |
421 | case TRUNC_DIV_EXPR: | |
422 | case CEIL_DIV_EXPR: | |
423 | case FLOOR_DIV_EXPR: | |
424 | case ROUND_DIV_EXPR: | |
425 | case EXACT_DIV_EXPR: | |
c3284718 RS |
426 | if (TYPE_SATURATING (type)) |
427 | return TYPE_UNSIGNED (type) ? usdiv_optab : ssdiv_optab; | |
26277d41 PB |
428 | return TYPE_UNSIGNED (type) ? udiv_optab : sdiv_optab; |
429 | ||
430 | case LSHIFT_EXPR: | |
8750672f | 431 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
432 | { |
433 | if (subtype == optab_vector) | |
2225b9f2 | 434 | return TYPE_SATURATING (type) ? unknown_optab : vashl_optab; |
71d46ca5 MM |
435 | |
436 | gcc_assert (subtype == optab_scalar); | |
437 | } | |
c3284718 RS |
438 | if (TYPE_SATURATING (type)) |
439 | return TYPE_UNSIGNED (type) ? usashl_optab : ssashl_optab; | |
26277d41 PB |
440 | return ashl_optab; |
441 | ||
442 | case RSHIFT_EXPR: | |
8750672f | 443 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
444 | { |
445 | if (subtype == optab_vector) | |
446 | return TYPE_UNSIGNED (type) ? vlshr_optab : vashr_optab; | |
447 | ||
448 | gcc_assert (subtype == optab_scalar); | |
449 | } | |
26277d41 PB |
450 | return TYPE_UNSIGNED (type) ? lshr_optab : ashr_optab; |
451 | ||
452 | case LROTATE_EXPR: | |
8750672f | 453 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
454 | { |
455 | if (subtype == optab_vector) | |
456 | return vrotl_optab; | |
457 | ||
458 | gcc_assert (subtype == optab_scalar); | |
459 | } | |
26277d41 PB |
460 | return rotl_optab; |
461 | ||
462 | case RROTATE_EXPR: | |
8750672f | 463 | if (TREE_CODE (type) == VECTOR_TYPE) |
71d46ca5 MM |
464 | { |
465 | if (subtype == optab_vector) | |
466 | return vrotr_optab; | |
467 | ||
468 | gcc_assert (subtype == optab_scalar); | |
469 | } | |
26277d41 PB |
470 | return rotr_optab; |
471 | ||
472 | case MAX_EXPR: | |
473 | return TYPE_UNSIGNED (type) ? umax_optab : smax_optab; | |
474 | ||
475 | case MIN_EXPR: | |
476 | return TYPE_UNSIGNED (type) ? umin_optab : smin_optab; | |
477 | ||
7ccf35ed DN |
478 | case REALIGN_LOAD_EXPR: |
479 | return vec_realign_load_optab; | |
480 | ||
20f06221 DN |
481 | case WIDEN_SUM_EXPR: |
482 | return TYPE_UNSIGNED (type) ? usum_widen_optab : ssum_widen_optab; | |
483 | ||
484 | case DOT_PROD_EXPR: | |
485 | return TYPE_UNSIGNED (type) ? udot_prod_optab : sdot_prod_optab; | |
486 | ||
79d652a5 CH |
487 | case SAD_EXPR: |
488 | return TYPE_UNSIGNED (type) ? usad_optab : ssad_optab; | |
489 | ||
0354c0c7 BS |
490 | case WIDEN_MULT_PLUS_EXPR: |
491 | return (TYPE_UNSIGNED (type) | |
492 | ? (TYPE_SATURATING (type) | |
493 | ? usmadd_widen_optab : umadd_widen_optab) | |
494 | : (TYPE_SATURATING (type) | |
495 | ? ssmadd_widen_optab : smadd_widen_optab)); | |
496 | ||
497 | case WIDEN_MULT_MINUS_EXPR: | |
498 | return (TYPE_UNSIGNED (type) | |
499 | ? (TYPE_SATURATING (type) | |
500 | ? usmsub_widen_optab : umsub_widen_optab) | |
501 | : (TYPE_SATURATING (type) | |
502 | ? ssmsub_widen_optab : smsub_widen_optab)); | |
503 | ||
16949072 RG |
504 | case FMA_EXPR: |
505 | return fma_optab; | |
506 | ||
61d3cdbb DN |
507 | case REDUC_MAX_EXPR: |
508 | return TYPE_UNSIGNED (type) ? reduc_umax_optab : reduc_smax_optab; | |
509 | ||
510 | case REDUC_MIN_EXPR: | |
511 | return TYPE_UNSIGNED (type) ? reduc_umin_optab : reduc_smin_optab; | |
512 | ||
513 | case REDUC_PLUS_EXPR: | |
a6b46ba2 DN |
514 | return TYPE_UNSIGNED (type) ? reduc_uplus_optab : reduc_splus_optab; |
515 | ||
516 | case VEC_LSHIFT_EXPR: | |
517 | return vec_shl_optab; | |
518 | ||
519 | case VEC_RSHIFT_EXPR: | |
520 | return vec_shr_optab; | |
61d3cdbb | 521 | |
89d67cca | 522 | case VEC_WIDEN_MULT_HI_EXPR: |
b8698a0f | 523 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
524 | vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; |
525 | ||
526 | case VEC_WIDEN_MULT_LO_EXPR: | |
b8698a0f | 527 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
528 | vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; |
529 | ||
3f30a9a6 RH |
530 | case VEC_WIDEN_MULT_EVEN_EXPR: |
531 | return TYPE_UNSIGNED (type) ? | |
532 | vec_widen_umult_even_optab : vec_widen_smult_even_optab; | |
533 | ||
534 | case VEC_WIDEN_MULT_ODD_EXPR: | |
535 | return TYPE_UNSIGNED (type) ? | |
536 | vec_widen_umult_odd_optab : vec_widen_smult_odd_optab; | |
537 | ||
36ba4aae IR |
538 | case VEC_WIDEN_LSHIFT_HI_EXPR: |
539 | return TYPE_UNSIGNED (type) ? | |
540 | vec_widen_ushiftl_hi_optab : vec_widen_sshiftl_hi_optab; | |
541 | ||
542 | case VEC_WIDEN_LSHIFT_LO_EXPR: | |
543 | return TYPE_UNSIGNED (type) ? | |
544 | vec_widen_ushiftl_lo_optab : vec_widen_sshiftl_lo_optab; | |
545 | ||
89d67cca | 546 | case VEC_UNPACK_HI_EXPR: |
8115817b | 547 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
548 | vec_unpacku_hi_optab : vec_unpacks_hi_optab; |
549 | ||
550 | case VEC_UNPACK_LO_EXPR: | |
b8698a0f | 551 | return TYPE_UNSIGNED (type) ? |
89d67cca DN |
552 | vec_unpacku_lo_optab : vec_unpacks_lo_optab; |
553 | ||
d9987fb4 UB |
554 | case VEC_UNPACK_FLOAT_HI_EXPR: |
555 | /* The signedness is determined from input operand. */ | |
556 | return TYPE_UNSIGNED (type) ? | |
557 | vec_unpacku_float_hi_optab : vec_unpacks_float_hi_optab; | |
558 | ||
559 | case VEC_UNPACK_FLOAT_LO_EXPR: | |
560 | /* The signedness is determined from input operand. */ | |
b8698a0f | 561 | return TYPE_UNSIGNED (type) ? |
d9987fb4 UB |
562 | vec_unpacku_float_lo_optab : vec_unpacks_float_lo_optab; |
563 | ||
8115817b UB |
564 | case VEC_PACK_TRUNC_EXPR: |
565 | return vec_pack_trunc_optab; | |
566 | ||
89d67cca DN |
567 | case VEC_PACK_SAT_EXPR: |
568 | return TYPE_UNSIGNED (type) ? vec_pack_usat_optab : vec_pack_ssat_optab; | |
8115817b | 569 | |
d9987fb4 | 570 | case VEC_PACK_FIX_TRUNC_EXPR: |
9f106823 | 571 | /* The signedness is determined from output operand. */ |
d9987fb4 UB |
572 | return TYPE_UNSIGNED (type) ? |
573 | vec_pack_ufix_trunc_optab : vec_pack_sfix_trunc_optab; | |
574 | ||
26277d41 PB |
575 | default: |
576 | break; | |
577 | } | |
578 | ||
eeef0e45 | 579 | trapv = INTEGRAL_TYPE_P (type) && TYPE_OVERFLOW_TRAPS (type); |
26277d41 PB |
580 | switch (code) |
581 | { | |
5be014d5 | 582 | case POINTER_PLUS_EXPR: |
26277d41 | 583 | case PLUS_EXPR: |
c3284718 RS |
584 | if (TYPE_SATURATING (type)) |
585 | return TYPE_UNSIGNED (type) ? usadd_optab : ssadd_optab; | |
26277d41 PB |
586 | return trapv ? addv_optab : add_optab; |
587 | ||
588 | case MINUS_EXPR: | |
c3284718 RS |
589 | if (TYPE_SATURATING (type)) |
590 | return TYPE_UNSIGNED (type) ? ussub_optab : sssub_optab; | |
26277d41 PB |
591 | return trapv ? subv_optab : sub_optab; |
592 | ||
593 | case MULT_EXPR: | |
c3284718 RS |
594 | if (TYPE_SATURATING (type)) |
595 | return TYPE_UNSIGNED (type) ? usmul_optab : ssmul_optab; | |
26277d41 PB |
596 | return trapv ? smulv_optab : smul_optab; |
597 | ||
598 | case NEGATE_EXPR: | |
c3284718 RS |
599 | if (TYPE_SATURATING (type)) |
600 | return TYPE_UNSIGNED (type) ? usneg_optab : ssneg_optab; | |
26277d41 PB |
601 | return trapv ? negv_optab : neg_optab; |
602 | ||
603 | case ABS_EXPR: | |
604 | return trapv ? absv_optab : abs_optab; | |
605 | ||
606 | default: | |
2225b9f2 | 607 | return unknown_optab; |
26277d41 PB |
608 | } |
609 | } | |
273a2526 | 610 | \f |
7ccf35ed | 611 | |
20f06221 DN |
612 | /* Expand vector widening operations. |
613 | ||
614 | There are two different classes of operations handled here: | |
615 | 1) Operations whose result is wider than all the arguments to the operation. | |
616 | Examples: VEC_UNPACK_HI/LO_EXPR, VEC_WIDEN_MULT_HI/LO_EXPR | |
617 | In this case OP0 and optionally OP1 would be initialized, | |
618 | but WIDE_OP wouldn't (not relevant for this case). | |
619 | 2) Operations whose result is of the same size as the last argument to the | |
620 | operation, but wider than all the other arguments to the operation. | |
621 | Examples: WIDEN_SUM_EXPR, VEC_DOT_PROD_EXPR. | |
622 | In the case WIDE_OP, OP0 and optionally OP1 would be initialized. | |
623 | ||
624 | E.g, when called to expand the following operations, this is how | |
625 | the arguments will be initialized: | |
626 | nops OP0 OP1 WIDE_OP | |
b8698a0f | 627 | widening-sum 2 oprnd0 - oprnd1 |
20f06221 DN |
628 | widening-dot-product 3 oprnd0 oprnd1 oprnd2 |
629 | widening-mult 2 oprnd0 oprnd1 - | |
630 | type-promotion (vec-unpack) 1 oprnd0 - - */ | |
631 | ||
632 | rtx | |
8e7aa1f9 MM |
633 | expand_widen_pattern_expr (sepops ops, rtx op0, rtx op1, rtx wide_op, |
634 | rtx target, int unsignedp) | |
b8698a0f | 635 | { |
a5c7d693 | 636 | struct expand_operand eops[4]; |
20f06221 | 637 | tree oprnd0, oprnd1, oprnd2; |
81f40b79 | 638 | enum machine_mode wmode = VOIDmode, tmode0, tmode1 = VOIDmode; |
20f06221 | 639 | optab widen_pattern_optab; |
a5c7d693 | 640 | enum insn_code icode; |
8e7aa1f9 | 641 | int nops = TREE_CODE_LENGTH (ops->code); |
a5c7d693 | 642 | int op; |
20f06221 | 643 | |
8e7aa1f9 | 644 | oprnd0 = ops->op0; |
20f06221 DN |
645 | tmode0 = TYPE_MODE (TREE_TYPE (oprnd0)); |
646 | widen_pattern_optab = | |
8e7aa1f9 | 647 | optab_for_tree_code (ops->code, TREE_TYPE (oprnd0), optab_default); |
0354c0c7 BS |
648 | if (ops->code == WIDEN_MULT_PLUS_EXPR |
649 | || ops->code == WIDEN_MULT_MINUS_EXPR) | |
5dfe80ba AS |
650 | icode = find_widening_optab_handler (widen_pattern_optab, |
651 | TYPE_MODE (TREE_TYPE (ops->op2)), | |
652 | tmode0, 0); | |
0354c0c7 | 653 | else |
a5c7d693 | 654 | icode = optab_handler (widen_pattern_optab, tmode0); |
20f06221 | 655 | gcc_assert (icode != CODE_FOR_nothing); |
20f06221 DN |
656 | |
657 | if (nops >= 2) | |
658 | { | |
8e7aa1f9 | 659 | oprnd1 = ops->op1; |
20f06221 | 660 | tmode1 = TYPE_MODE (TREE_TYPE (oprnd1)); |
20f06221 DN |
661 | } |
662 | ||
663 | /* The last operand is of a wider mode than the rest of the operands. */ | |
664 | if (nops == 2) | |
a5c7d693 | 665 | wmode = tmode1; |
20f06221 DN |
666 | else if (nops == 3) |
667 | { | |
668 | gcc_assert (tmode1 == tmode0); | |
669 | gcc_assert (op1); | |
8e7aa1f9 | 670 | oprnd2 = ops->op2; |
20f06221 | 671 | wmode = TYPE_MODE (TREE_TYPE (oprnd2)); |
20f06221 DN |
672 | } |
673 | ||
a5c7d693 RS |
674 | op = 0; |
675 | create_output_operand (&eops[op++], target, TYPE_MODE (ops->type)); | |
676 | create_convert_operand_from (&eops[op++], op0, tmode0, unsignedp); | |
20f06221 | 677 | if (op1) |
a5c7d693 | 678 | create_convert_operand_from (&eops[op++], op1, tmode1, unsignedp); |
20f06221 | 679 | if (wide_op) |
a5c7d693 RS |
680 | create_convert_operand_from (&eops[op++], wide_op, wmode, unsignedp); |
681 | expand_insn (icode, op, eops); | |
682 | return eops[0].value; | |
20f06221 DN |
683 | } |
684 | ||
7ccf35ed DN |
685 | /* Generate code to perform an operation specified by TERNARY_OPTAB |
686 | on operands OP0, OP1 and OP2, with result having machine-mode MODE. | |
687 | ||
688 | UNSIGNEDP is for the case where we have to widen the operands | |
689 | to perform the operation. It says to use zero-extension. | |
690 | ||
691 | If TARGET is nonzero, the value | |
692 | is generated there, if it is convenient to do so. | |
693 | In all cases an rtx is returned for the locus of the value; | |
694 | this may or may not be TARGET. */ | |
695 | ||
696 | rtx | |
c414ac1d EC |
697 | expand_ternary_op (enum machine_mode mode, optab ternary_optab, rtx op0, |
698 | rtx op1, rtx op2, rtx target, int unsignedp) | |
7ccf35ed | 699 | { |
a5c7d693 RS |
700 | struct expand_operand ops[4]; |
701 | enum insn_code icode = optab_handler (ternary_optab, mode); | |
7ccf35ed | 702 | |
947131ba | 703 | gcc_assert (optab_handler (ternary_optab, mode) != CODE_FOR_nothing); |
7ccf35ed | 704 | |
a5c7d693 RS |
705 | create_output_operand (&ops[0], target, mode); |
706 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
707 | create_convert_operand_from (&ops[2], op1, mode, unsignedp); | |
708 | create_convert_operand_from (&ops[3], op2, mode, unsignedp); | |
709 | expand_insn (icode, 4, ops); | |
710 | return ops[0].value; | |
7ccf35ed DN |
711 | } |
712 | ||
713 | ||
273a2526 RS |
714 | /* Like expand_binop, but return a constant rtx if the result can be |
715 | calculated at compile time. The arguments and return value are | |
716 | otherwise the same as for expand_binop. */ | |
717 | ||
3bdb97b8 | 718 | rtx |
273a2526 RS |
719 | simplify_expand_binop (enum machine_mode mode, optab binoptab, |
720 | rtx op0, rtx op1, rtx target, int unsignedp, | |
721 | enum optab_methods methods) | |
722 | { | |
723 | if (CONSTANT_P (op0) && CONSTANT_P (op1)) | |
68162a97 | 724 | { |
19b5fafb RH |
725 | rtx x = simplify_binary_operation (optab_to_code (binoptab), |
726 | mode, op0, op1); | |
68162a97 ILT |
727 | if (x) |
728 | return x; | |
729 | } | |
730 | ||
731 | return expand_binop (mode, binoptab, op0, op1, target, unsignedp, methods); | |
273a2526 RS |
732 | } |
733 | ||
734 | /* Like simplify_expand_binop, but always put the result in TARGET. | |
735 | Return true if the expansion succeeded. */ | |
736 | ||
bef5d8b6 | 737 | bool |
273a2526 RS |
738 | force_expand_binop (enum machine_mode mode, optab binoptab, |
739 | rtx op0, rtx op1, rtx target, int unsignedp, | |
740 | enum optab_methods methods) | |
741 | { | |
742 | rtx x = simplify_expand_binop (mode, binoptab, op0, op1, | |
743 | target, unsignedp, methods); | |
744 | if (x == 0) | |
745 | return false; | |
746 | if (x != target) | |
747 | emit_move_insn (target, x); | |
748 | return true; | |
749 | } | |
750 | ||
a6b46ba2 DN |
751 | /* Generate insns for VEC_LSHIFT_EXPR, VEC_RSHIFT_EXPR. */ |
752 | ||
753 | rtx | |
8e7aa1f9 | 754 | expand_vec_shift_expr (sepops ops, rtx target) |
a6b46ba2 | 755 | { |
a5c7d693 | 756 | struct expand_operand eops[3]; |
a6b46ba2 DN |
757 | enum insn_code icode; |
758 | rtx rtx_op1, rtx_op2; | |
8e7aa1f9 MM |
759 | enum machine_mode mode = TYPE_MODE (ops->type); |
760 | tree vec_oprnd = ops->op0; | |
761 | tree shift_oprnd = ops->op1; | |
a6b46ba2 | 762 | optab shift_optab; |
a6b46ba2 | 763 | |
8e7aa1f9 | 764 | switch (ops->code) |
a6b46ba2 DN |
765 | { |
766 | case VEC_RSHIFT_EXPR: | |
767 | shift_optab = vec_shr_optab; | |
768 | break; | |
769 | case VEC_LSHIFT_EXPR: | |
770 | shift_optab = vec_shl_optab; | |
771 | break; | |
772 | default: | |
773 | gcc_unreachable (); | |
774 | } | |
775 | ||
947131ba | 776 | icode = optab_handler (shift_optab, mode); |
a6b46ba2 DN |
777 | gcc_assert (icode != CODE_FOR_nothing); |
778 | ||
49452c07 | 779 | rtx_op1 = expand_normal (vec_oprnd); |
49452c07 | 780 | rtx_op2 = expand_normal (shift_oprnd); |
a6b46ba2 | 781 | |
a5c7d693 RS |
782 | create_output_operand (&eops[0], target, mode); |
783 | create_input_operand (&eops[1], rtx_op1, GET_MODE (rtx_op1)); | |
784 | create_convert_operand_from_type (&eops[2], rtx_op2, TREE_TYPE (shift_oprnd)); | |
785 | expand_insn (icode, 3, eops); | |
a6b46ba2 | 786 | |
a5c7d693 | 787 | return eops[0].value; |
a6b46ba2 DN |
788 | } |
789 | ||
bdc3ee5d RH |
790 | /* Create a new vector value in VMODE with all elements set to OP. The |
791 | mode of OP must be the element mode of VMODE. If OP is a constant, | |
792 | then the return value will be a constant. */ | |
793 | ||
794 | static rtx | |
795 | expand_vector_broadcast (enum machine_mode vmode, rtx op) | |
796 | { | |
797 | enum insn_code icode; | |
798 | rtvec vec; | |
799 | rtx ret; | |
800 | int i, n; | |
801 | ||
802 | gcc_checking_assert (VECTOR_MODE_P (vmode)); | |
803 | ||
804 | n = GET_MODE_NUNITS (vmode); | |
805 | vec = rtvec_alloc (n); | |
806 | for (i = 0; i < n; ++i) | |
807 | RTVEC_ELT (vec, i) = op; | |
808 | ||
809 | if (CONSTANT_P (op)) | |
810 | return gen_rtx_CONST_VECTOR (vmode, vec); | |
811 | ||
812 | /* ??? If the target doesn't have a vec_init, then we have no easy way | |
813 | of performing this operation. Most of this sort of generic support | |
814 | is hidden away in the vector lowering support in gimple. */ | |
815 | icode = optab_handler (vec_init_optab, vmode); | |
816 | if (icode == CODE_FOR_nothing) | |
817 | return NULL; | |
818 | ||
819 | ret = gen_reg_rtx (vmode); | |
820 | emit_insn (GEN_FCN (icode) (ret, gen_rtx_PARALLEL (vmode, vec))); | |
821 | ||
822 | return ret; | |
823 | } | |
824 | ||
273a2526 RS |
825 | /* This subroutine of expand_doubleword_shift handles the cases in which |
826 | the effective shift value is >= BITS_PER_WORD. The arguments and return | |
827 | value are the same as for the parent routine, except that SUPERWORD_OP1 | |
828 | is the shift count to use when shifting OUTOF_INPUT into INTO_TARGET. | |
829 | INTO_TARGET may be null if the caller has decided to calculate it. */ | |
830 | ||
831 | static bool | |
832 | expand_superword_shift (optab binoptab, rtx outof_input, rtx superword_op1, | |
833 | rtx outof_target, rtx into_target, | |
834 | int unsignedp, enum optab_methods methods) | |
835 | { | |
836 | if (into_target != 0) | |
837 | if (!force_expand_binop (word_mode, binoptab, outof_input, superword_op1, | |
838 | into_target, unsignedp, methods)) | |
839 | return false; | |
840 | ||
841 | if (outof_target != 0) | |
842 | { | |
843 | /* For a signed right shift, we must fill OUTOF_TARGET with copies | |
844 | of the sign bit, otherwise we must fill it with zeros. */ | |
845 | if (binoptab != ashr_optab) | |
846 | emit_move_insn (outof_target, CONST0_RTX (word_mode)); | |
847 | else | |
848 | if (!force_expand_binop (word_mode, binoptab, | |
849 | outof_input, GEN_INT (BITS_PER_WORD - 1), | |
850 | outof_target, unsignedp, methods)) | |
851 | return false; | |
852 | } | |
853 | return true; | |
854 | } | |
855 | ||
856 | /* This subroutine of expand_doubleword_shift handles the cases in which | |
857 | the effective shift value is < BITS_PER_WORD. The arguments and return | |
858 | value are the same as for the parent routine. */ | |
859 | ||
860 | static bool | |
861 | expand_subword_shift (enum machine_mode op1_mode, optab binoptab, | |
862 | rtx outof_input, rtx into_input, rtx op1, | |
863 | rtx outof_target, rtx into_target, | |
864 | int unsignedp, enum optab_methods methods, | |
865 | unsigned HOST_WIDE_INT shift_mask) | |
866 | { | |
867 | optab reverse_unsigned_shift, unsigned_shift; | |
868 | rtx tmp, carries; | |
869 | ||
870 | reverse_unsigned_shift = (binoptab == ashl_optab ? lshr_optab : ashl_optab); | |
871 | unsigned_shift = (binoptab == ashl_optab ? ashl_optab : lshr_optab); | |
872 | ||
873 | /* The low OP1 bits of INTO_TARGET come from the high bits of OUTOF_INPUT. | |
874 | We therefore need to shift OUTOF_INPUT by (BITS_PER_WORD - OP1) bits in | |
875 | the opposite direction to BINOPTAB. */ | |
876 | if (CONSTANT_P (op1) || shift_mask >= BITS_PER_WORD) | |
877 | { | |
878 | carries = outof_input; | |
807e902e KZ |
879 | tmp = immed_wide_int_const (wi::shwi (BITS_PER_WORD, |
880 | op1_mode), op1_mode); | |
273a2526 RS |
881 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, |
882 | 0, true, methods); | |
883 | } | |
884 | else | |
885 | { | |
886 | /* We must avoid shifting by BITS_PER_WORD bits since that is either | |
887 | the same as a zero shift (if shift_mask == BITS_PER_WORD - 1) or | |
b01d837f | 888 | has unknown behavior. Do a single shift first, then shift by the |
273a2526 RS |
889 | remainder. It's OK to use ~OP1 as the remainder if shift counts |
890 | are truncated to the mode size. */ | |
891 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
892 | outof_input, const1_rtx, 0, unsignedp, methods); | |
893 | if (shift_mask == BITS_PER_WORD - 1) | |
894 | { | |
807e902e KZ |
895 | tmp = immed_wide_int_const |
896 | (wi::minus_one (GET_MODE_PRECISION (op1_mode)), op1_mode); | |
273a2526 RS |
897 | tmp = simplify_expand_binop (op1_mode, xor_optab, op1, tmp, |
898 | 0, true, methods); | |
899 | } | |
900 | else | |
901 | { | |
807e902e KZ |
902 | tmp = immed_wide_int_const (wi::shwi (BITS_PER_WORD - 1, |
903 | op1_mode), op1_mode); | |
273a2526 RS |
904 | tmp = simplify_expand_binop (op1_mode, sub_optab, tmp, op1, |
905 | 0, true, methods); | |
906 | } | |
907 | } | |
908 | if (tmp == 0 || carries == 0) | |
909 | return false; | |
910 | carries = expand_binop (word_mode, reverse_unsigned_shift, | |
911 | carries, tmp, 0, unsignedp, methods); | |
912 | if (carries == 0) | |
913 | return false; | |
914 | ||
915 | /* Shift INTO_INPUT logically by OP1. This is the last use of INTO_INPUT | |
916 | so the result can go directly into INTO_TARGET if convenient. */ | |
917 | tmp = expand_binop (word_mode, unsigned_shift, into_input, op1, | |
918 | into_target, unsignedp, methods); | |
919 | if (tmp == 0) | |
920 | return false; | |
921 | ||
922 | /* Now OR in the bits carried over from OUTOF_INPUT. */ | |
923 | if (!force_expand_binop (word_mode, ior_optab, tmp, carries, | |
924 | into_target, unsignedp, methods)) | |
925 | return false; | |
926 | ||
927 | /* Use a standard word_mode shift for the out-of half. */ | |
928 | if (outof_target != 0) | |
929 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
930 | outof_target, unsignedp, methods)) | |
931 | return false; | |
932 | ||
933 | return true; | |
934 | } | |
935 | ||
936 | ||
937 | #ifdef HAVE_conditional_move | |
938 | /* Try implementing expand_doubleword_shift using conditional moves. | |
939 | The shift is by < BITS_PER_WORD if (CMP_CODE CMP1 CMP2) is true, | |
940 | otherwise it is by >= BITS_PER_WORD. SUBWORD_OP1 and SUPERWORD_OP1 | |
941 | are the shift counts to use in the former and latter case. All other | |
942 | arguments are the same as the parent routine. */ | |
943 | ||
944 | static bool | |
945 | expand_doubleword_shift_condmove (enum machine_mode op1_mode, optab binoptab, | |
946 | enum rtx_code cmp_code, rtx cmp1, rtx cmp2, | |
947 | rtx outof_input, rtx into_input, | |
948 | rtx subword_op1, rtx superword_op1, | |
949 | rtx outof_target, rtx into_target, | |
950 | int unsignedp, enum optab_methods methods, | |
951 | unsigned HOST_WIDE_INT shift_mask) | |
952 | { | |
953 | rtx outof_superword, into_superword; | |
954 | ||
955 | /* Put the superword version of the output into OUTOF_SUPERWORD and | |
956 | INTO_SUPERWORD. */ | |
957 | outof_superword = outof_target != 0 ? gen_reg_rtx (word_mode) : 0; | |
958 | if (outof_target != 0 && subword_op1 == superword_op1) | |
959 | { | |
960 | /* The value INTO_TARGET >> SUBWORD_OP1, which we later store in | |
961 | OUTOF_TARGET, is the same as the value of INTO_SUPERWORD. */ | |
962 | into_superword = outof_target; | |
963 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
964 | outof_superword, 0, unsignedp, methods)) | |
965 | return false; | |
966 | } | |
967 | else | |
968 | { | |
969 | into_superword = gen_reg_rtx (word_mode); | |
970 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
971 | outof_superword, into_superword, | |
972 | unsignedp, methods)) | |
973 | return false; | |
974 | } | |
26277d41 | 975 | |
273a2526 RS |
976 | /* Put the subword version directly in OUTOF_TARGET and INTO_TARGET. */ |
977 | if (!expand_subword_shift (op1_mode, binoptab, | |
978 | outof_input, into_input, subword_op1, | |
979 | outof_target, into_target, | |
980 | unsignedp, methods, shift_mask)) | |
981 | return false; | |
982 | ||
983 | /* Select between them. Do the INTO half first because INTO_SUPERWORD | |
984 | might be the current value of OUTOF_TARGET. */ | |
985 | if (!emit_conditional_move (into_target, cmp_code, cmp1, cmp2, op1_mode, | |
986 | into_target, into_superword, word_mode, false)) | |
987 | return false; | |
988 | ||
989 | if (outof_target != 0) | |
990 | if (!emit_conditional_move (outof_target, cmp_code, cmp1, cmp2, op1_mode, | |
991 | outof_target, outof_superword, | |
992 | word_mode, false)) | |
993 | return false; | |
994 | ||
995 | return true; | |
996 | } | |
997 | #endif | |
998 | ||
999 | /* Expand a doubleword shift (ashl, ashr or lshr) using word-mode shifts. | |
1000 | OUTOF_INPUT and INTO_INPUT are the two word-sized halves of the first | |
1001 | input operand; the shift moves bits in the direction OUTOF_INPUT-> | |
1002 | INTO_TARGET. OUTOF_TARGET and INTO_TARGET are the equivalent words | |
1003 | of the target. OP1 is the shift count and OP1_MODE is its mode. | |
1004 | If OP1 is constant, it will have been truncated as appropriate | |
1005 | and is known to be nonzero. | |
1006 | ||
1007 | If SHIFT_MASK is zero, the result of word shifts is undefined when the | |
1008 | shift count is outside the range [0, BITS_PER_WORD). This routine must | |
1009 | avoid generating such shifts for OP1s in the range [0, BITS_PER_WORD * 2). | |
1010 | ||
1011 | If SHIFT_MASK is nonzero, all word-mode shift counts are effectively | |
1012 | masked by it and shifts in the range [BITS_PER_WORD, SHIFT_MASK) will | |
1013 | fill with zeros or sign bits as appropriate. | |
1014 | ||
2a7e31df | 1015 | If SHIFT_MASK is BITS_PER_WORD - 1, this routine will synthesize |
273a2526 RS |
1016 | a doubleword shift whose equivalent mask is BITS_PER_WORD * 2 - 1. |
1017 | Doing this preserves semantics required by SHIFT_COUNT_TRUNCATED. | |
1018 | In all other cases, shifts by values outside [0, BITS_PER_UNIT * 2) | |
1019 | are undefined. | |
1020 | ||
1021 | BINOPTAB, UNSIGNEDP and METHODS are as for expand_binop. This function | |
1022 | may not use INTO_INPUT after modifying INTO_TARGET, and similarly for | |
1023 | OUTOF_INPUT and OUTOF_TARGET. OUTOF_TARGET can be null if the parent | |
1024 | function wants to calculate it itself. | |
1025 | ||
1026 | Return true if the shift could be successfully synthesized. */ | |
1027 | ||
1028 | static bool | |
1029 | expand_doubleword_shift (enum machine_mode op1_mode, optab binoptab, | |
1030 | rtx outof_input, rtx into_input, rtx op1, | |
1031 | rtx outof_target, rtx into_target, | |
1032 | int unsignedp, enum optab_methods methods, | |
1033 | unsigned HOST_WIDE_INT shift_mask) | |
1034 | { | |
1035 | rtx superword_op1, tmp, cmp1, cmp2; | |
1036 | rtx subword_label, done_label; | |
1037 | enum rtx_code cmp_code; | |
1038 | ||
1039 | /* See if word-mode shifts by BITS_PER_WORD...BITS_PER_WORD * 2 - 1 will | |
1040 | fill the result with sign or zero bits as appropriate. If so, the value | |
1041 | of OUTOF_TARGET will always be (SHIFT OUTOF_INPUT OP1). Recursively call | |
1042 | this routine to calculate INTO_TARGET (which depends on both OUTOF_INPUT | |
1043 | and INTO_INPUT), then emit code to set up OUTOF_TARGET. | |
1044 | ||
1045 | This isn't worthwhile for constant shifts since the optimizers will | |
1046 | cope better with in-range shift counts. */ | |
1047 | if (shift_mask >= BITS_PER_WORD | |
1048 | && outof_target != 0 | |
1049 | && !CONSTANT_P (op1)) | |
1050 | { | |
1051 | if (!expand_doubleword_shift (op1_mode, binoptab, | |
1052 | outof_input, into_input, op1, | |
1053 | 0, into_target, | |
1054 | unsignedp, methods, shift_mask)) | |
1055 | return false; | |
1056 | if (!force_expand_binop (word_mode, binoptab, outof_input, op1, | |
1057 | outof_target, unsignedp, methods)) | |
1058 | return false; | |
1059 | return true; | |
1060 | } | |
1061 | ||
1062 | /* Set CMP_CODE, CMP1 and CMP2 so that the rtx (CMP_CODE CMP1 CMP2) | |
1063 | is true when the effective shift value is less than BITS_PER_WORD. | |
1064 | Set SUPERWORD_OP1 to the shift count that should be used to shift | |
1065 | OUTOF_INPUT into INTO_TARGET when the condition is false. */ | |
807e902e | 1066 | tmp = immed_wide_int_const (wi::shwi (BITS_PER_WORD, op1_mode), op1_mode); |
273a2526 RS |
1067 | if (!CONSTANT_P (op1) && shift_mask == BITS_PER_WORD - 1) |
1068 | { | |
1069 | /* Set CMP1 to OP1 & BITS_PER_WORD. The result is zero iff OP1 | |
1070 | is a subword shift count. */ | |
1071 | cmp1 = simplify_expand_binop (op1_mode, and_optab, op1, tmp, | |
1072 | 0, true, methods); | |
1073 | cmp2 = CONST0_RTX (op1_mode); | |
1074 | cmp_code = EQ; | |
1075 | superword_op1 = op1; | |
1076 | } | |
1077 | else | |
1078 | { | |
1079 | /* Set CMP1 to OP1 - BITS_PER_WORD. */ | |
1080 | cmp1 = simplify_expand_binop (op1_mode, sub_optab, op1, tmp, | |
1081 | 0, true, methods); | |
1082 | cmp2 = CONST0_RTX (op1_mode); | |
1083 | cmp_code = LT; | |
1084 | superword_op1 = cmp1; | |
1085 | } | |
1086 | if (cmp1 == 0) | |
1087 | return false; | |
1088 | ||
1089 | /* If we can compute the condition at compile time, pick the | |
1090 | appropriate subroutine. */ | |
1091 | tmp = simplify_relational_operation (cmp_code, SImode, op1_mode, cmp1, cmp2); | |
481683e1 | 1092 | if (tmp != 0 && CONST_INT_P (tmp)) |
273a2526 RS |
1093 | { |
1094 | if (tmp == const0_rtx) | |
1095 | return expand_superword_shift (binoptab, outof_input, superword_op1, | |
1096 | outof_target, into_target, | |
1097 | unsignedp, methods); | |
1098 | else | |
1099 | return expand_subword_shift (op1_mode, binoptab, | |
1100 | outof_input, into_input, op1, | |
1101 | outof_target, into_target, | |
1102 | unsignedp, methods, shift_mask); | |
1103 | } | |
1104 | ||
1105 | #ifdef HAVE_conditional_move | |
1106 | /* Try using conditional moves to generate straight-line code. */ | |
1107 | { | |
1108 | rtx start = get_last_insn (); | |
1109 | if (expand_doubleword_shift_condmove (op1_mode, binoptab, | |
1110 | cmp_code, cmp1, cmp2, | |
1111 | outof_input, into_input, | |
1112 | op1, superword_op1, | |
1113 | outof_target, into_target, | |
1114 | unsignedp, methods, shift_mask)) | |
1115 | return true; | |
1116 | delete_insns_since (start); | |
1117 | } | |
1118 | #endif | |
1119 | ||
1120 | /* As a last resort, use branches to select the correct alternative. */ | |
1121 | subword_label = gen_label_rtx (); | |
1122 | done_label = gen_label_rtx (); | |
1123 | ||
2763a67e | 1124 | NO_DEFER_POP; |
273a2526 | 1125 | do_compare_rtx_and_jump (cmp1, cmp2, cmp_code, false, op1_mode, |
40e90eac | 1126 | 0, 0, subword_label, -1); |
2763a67e | 1127 | OK_DEFER_POP; |
273a2526 RS |
1128 | |
1129 | if (!expand_superword_shift (binoptab, outof_input, superword_op1, | |
1130 | outof_target, into_target, | |
1131 | unsignedp, methods)) | |
1132 | return false; | |
1133 | ||
1134 | emit_jump_insn (gen_jump (done_label)); | |
1135 | emit_barrier (); | |
1136 | emit_label (subword_label); | |
1137 | ||
1138 | if (!expand_subword_shift (op1_mode, binoptab, | |
1139 | outof_input, into_input, op1, | |
1140 | outof_target, into_target, | |
1141 | unsignedp, methods, shift_mask)) | |
1142 | return false; | |
1143 | ||
1144 | emit_label (done_label); | |
1145 | return true; | |
1146 | } | |
c64f913e | 1147 | \f |
f927760b RS |
1148 | /* Subroutine of expand_binop. Perform a double word multiplication of |
1149 | operands OP0 and OP1 both of mode MODE, which is exactly twice as wide | |
1150 | as the target's word_mode. This function return NULL_RTX if anything | |
1151 | goes wrong, in which case it may have already emitted instructions | |
1152 | which need to be deleted. | |
1153 | ||
1154 | If we want to multiply two two-word values and have normal and widening | |
1155 | multiplies of single-word values, we can do this with three smaller | |
d70dcf29 | 1156 | multiplications. |
f927760b RS |
1157 | |
1158 | The multiplication proceeds as follows: | |
1159 | _______________________ | |
1160 | [__op0_high_|__op0_low__] | |
1161 | _______________________ | |
1162 | * [__op1_high_|__op1_low__] | |
1163 | _______________________________________________ | |
1164 | _______________________ | |
1165 | (1) [__op0_low__*__op1_low__] | |
1166 | _______________________ | |
1167 | (2a) [__op0_low__*__op1_high_] | |
1168 | _______________________ | |
1169 | (2b) [__op0_high_*__op1_low__] | |
1170 | _______________________ | |
1171 | (3) [__op0_high_*__op1_high_] | |
1172 | ||
1173 | ||
1174 | This gives a 4-word result. Since we are only interested in the | |
1175 | lower 2 words, partial result (3) and the upper words of (2a) and | |
1176 | (2b) don't need to be calculated. Hence (2a) and (2b) can be | |
1177 | calculated using non-widening multiplication. | |
1178 | ||
1179 | (1), however, needs to be calculated with an unsigned widening | |
1180 | multiplication. If this operation is not directly supported we | |
1181 | try using a signed widening multiplication and adjust the result. | |
1182 | This adjustment works as follows: | |
1183 | ||
1184 | If both operands are positive then no adjustment is needed. | |
1185 | ||
1186 | If the operands have different signs, for example op0_low < 0 and | |
1187 | op1_low >= 0, the instruction treats the most significant bit of | |
1188 | op0_low as a sign bit instead of a bit with significance | |
1189 | 2**(BITS_PER_WORD-1), i.e. the instruction multiplies op1_low | |
1190 | with 2**BITS_PER_WORD - op0_low, and two's complements the | |
1191 | result. Conclusion: We need to add op1_low * 2**BITS_PER_WORD to | |
1192 | the result. | |
1193 | ||
1194 | Similarly, if both operands are negative, we need to add | |
1195 | (op0_low + op1_low) * 2**BITS_PER_WORD. | |
1196 | ||
1197 | We use a trick to adjust quickly. We logically shift op0_low right | |
1198 | (op1_low) BITS_PER_WORD-1 steps to get 0 or 1, and add this to | |
1199 | op0_high (op1_high) before it is used to calculate 2b (2a). If no | |
1200 | logical shift exists, we do an arithmetic right shift and subtract | |
1201 | the 0 or -1. */ | |
1202 | ||
1203 | static rtx | |
1204 | expand_doubleword_mult (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
1205 | bool umulp, enum optab_methods methods) | |
1206 | { | |
1207 | int low = (WORDS_BIG_ENDIAN ? 1 : 0); | |
1208 | int high = (WORDS_BIG_ENDIAN ? 0 : 1); | |
1209 | rtx wordm1 = umulp ? NULL_RTX : GEN_INT (BITS_PER_WORD - 1); | |
1210 | rtx product, adjust, product_high, temp; | |
1211 | ||
1212 | rtx op0_high = operand_subword_force (op0, high, mode); | |
1213 | rtx op0_low = operand_subword_force (op0, low, mode); | |
1214 | rtx op1_high = operand_subword_force (op1, high, mode); | |
1215 | rtx op1_low = operand_subword_force (op1, low, mode); | |
1216 | ||
1217 | /* If we're using an unsigned multiply to directly compute the product | |
1218 | of the low-order words of the operands and perform any required | |
1219 | adjustments of the operands, we begin by trying two more multiplications | |
1220 | and then computing the appropriate sum. | |
1221 | ||
1222 | We have checked above that the required addition is provided. | |
1223 | Full-word addition will normally always succeed, especially if | |
1224 | it is provided at all, so we don't worry about its failure. The | |
1225 | multiplication may well fail, however, so we do handle that. */ | |
1226 | ||
1227 | if (!umulp) | |
1228 | { | |
1229 | /* ??? This could be done with emit_store_flag where available. */ | |
1230 | temp = expand_binop (word_mode, lshr_optab, op0_low, wordm1, | |
1231 | NULL_RTX, 1, methods); | |
1232 | if (temp) | |
1233 | op0_high = expand_binop (word_mode, add_optab, op0_high, temp, | |
69f39b11 | 1234 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1235 | else |
1236 | { | |
1237 | temp = expand_binop (word_mode, ashr_optab, op0_low, wordm1, | |
1238 | NULL_RTX, 0, methods); | |
1239 | if (!temp) | |
1240 | return NULL_RTX; | |
1241 | op0_high = expand_binop (word_mode, sub_optab, op0_high, temp, | |
69f39b11 | 1242 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1243 | } |
1244 | ||
1245 | if (!op0_high) | |
1246 | return NULL_RTX; | |
1247 | } | |
1248 | ||
1249 | adjust = expand_binop (word_mode, smul_optab, op0_high, op1_low, | |
1250 | NULL_RTX, 0, OPTAB_DIRECT); | |
1251 | if (!adjust) | |
1252 | return NULL_RTX; | |
1253 | ||
1254 | /* OP0_HIGH should now be dead. */ | |
1255 | ||
1256 | if (!umulp) | |
1257 | { | |
1258 | /* ??? This could be done with emit_store_flag where available. */ | |
1259 | temp = expand_binop (word_mode, lshr_optab, op1_low, wordm1, | |
1260 | NULL_RTX, 1, methods); | |
1261 | if (temp) | |
1262 | op1_high = expand_binop (word_mode, add_optab, op1_high, temp, | |
69f39b11 | 1263 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1264 | else |
1265 | { | |
1266 | temp = expand_binop (word_mode, ashr_optab, op1_low, wordm1, | |
1267 | NULL_RTX, 0, methods); | |
1268 | if (!temp) | |
1269 | return NULL_RTX; | |
1270 | op1_high = expand_binop (word_mode, sub_optab, op1_high, temp, | |
69f39b11 | 1271 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1272 | } |
1273 | ||
1274 | if (!op1_high) | |
1275 | return NULL_RTX; | |
1276 | } | |
1277 | ||
1278 | temp = expand_binop (word_mode, smul_optab, op1_high, op0_low, | |
1279 | NULL_RTX, 0, OPTAB_DIRECT); | |
1280 | if (!temp) | |
1281 | return NULL_RTX; | |
1282 | ||
1283 | /* OP1_HIGH should now be dead. */ | |
1284 | ||
1285 | adjust = expand_binop (word_mode, add_optab, adjust, temp, | |
c701e857 | 1286 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1287 | |
1288 | if (target && !REG_P (target)) | |
1289 | target = NULL_RTX; | |
1290 | ||
1291 | if (umulp) | |
1292 | product = expand_binop (mode, umul_widen_optab, op0_low, op1_low, | |
1293 | target, 1, OPTAB_DIRECT); | |
1294 | else | |
1295 | product = expand_binop (mode, smul_widen_optab, op0_low, op1_low, | |
1296 | target, 1, OPTAB_DIRECT); | |
1297 | ||
1298 | if (!product) | |
1299 | return NULL_RTX; | |
1300 | ||
1301 | product_high = operand_subword (product, high, 1, mode); | |
1302 | adjust = expand_binop (word_mode, add_optab, product_high, adjust, | |
c701e857 | 1303 | NULL_RTX, 0, OPTAB_DIRECT); |
f927760b RS |
1304 | emit_move_insn (product_high, adjust); |
1305 | return product; | |
1306 | } | |
1307 | \f | |
ef89d648 ZW |
1308 | /* Wrapper around expand_binop which takes an rtx code to specify |
1309 | the operation to perform, not an optab pointer. All other | |
1310 | arguments are the same. */ | |
1311 | rtx | |
0c20a65f AJ |
1312 | expand_simple_binop (enum machine_mode mode, enum rtx_code code, rtx op0, |
1313 | rtx op1, rtx target, int unsignedp, | |
1314 | enum optab_methods methods) | |
ef89d648 | 1315 | { |
19b5fafb | 1316 | optab binop = code_to_optab (code); |
e3feb571 | 1317 | gcc_assert (binop); |
ef89d648 ZW |
1318 | |
1319 | return expand_binop (mode, binop, op0, op1, target, unsignedp, methods); | |
1320 | } | |
1321 | ||
665d18c6 PB |
1322 | /* Return whether OP0 and OP1 should be swapped when expanding a commutative |
1323 | binop. Order them according to commutative_operand_precedence and, if | |
1324 | possible, try to put TARGET or a pseudo first. */ | |
1325 | static bool | |
1326 | swap_commutative_operands_with_target (rtx target, rtx op0, rtx op1) | |
1327 | { | |
1328 | int op0_prec = commutative_operand_precedence (op0); | |
1329 | int op1_prec = commutative_operand_precedence (op1); | |
1330 | ||
1331 | if (op0_prec < op1_prec) | |
1332 | return true; | |
1333 | ||
1334 | if (op0_prec > op1_prec) | |
1335 | return false; | |
1336 | ||
1337 | /* With equal precedence, both orders are ok, but it is better if the | |
1338 | first operand is TARGET, or if both TARGET and OP0 are pseudos. */ | |
1339 | if (target == 0 || REG_P (target)) | |
1340 | return (REG_P (op1) && !REG_P (op0)) || target == op1; | |
1341 | else | |
1342 | return rtx_equal_p (op1, target); | |
1343 | } | |
1344 | ||
62442ab9 RS |
1345 | /* Return true if BINOPTAB implements a shift operation. */ |
1346 | ||
1347 | static bool | |
1348 | shift_optab_p (optab binoptab) | |
1349 | { | |
19b5fafb | 1350 | switch (optab_to_code (binoptab)) |
62442ab9 RS |
1351 | { |
1352 | case ASHIFT: | |
0f996086 CF |
1353 | case SS_ASHIFT: |
1354 | case US_ASHIFT: | |
62442ab9 RS |
1355 | case ASHIFTRT: |
1356 | case LSHIFTRT: | |
1357 | case ROTATE: | |
1358 | case ROTATERT: | |
1359 | return true; | |
1360 | ||
1361 | default: | |
1362 | return false; | |
1363 | } | |
1364 | } | |
1365 | ||
15dc95cb | 1366 | /* Return true if BINOPTAB implements a commutative binary operation. */ |
62442ab9 RS |
1367 | |
1368 | static bool | |
1369 | commutative_optab_p (optab binoptab) | |
1370 | { | |
19b5fafb | 1371 | return (GET_RTX_CLASS (optab_to_code (binoptab)) == RTX_COMM_ARITH |
62442ab9 RS |
1372 | || binoptab == smul_widen_optab |
1373 | || binoptab == umul_widen_optab | |
1374 | || binoptab == smul_highpart_optab | |
1375 | || binoptab == umul_highpart_optab); | |
1376 | } | |
1377 | ||
68f932c4 | 1378 | /* X is to be used in mode MODE as operand OPN to BINOPTAB. If we're |
62442ab9 RS |
1379 | optimizing, and if the operand is a constant that costs more than |
1380 | 1 instruction, force the constant into a register and return that | |
1381 | register. Return X otherwise. UNSIGNEDP says whether X is unsigned. */ | |
1382 | ||
1383 | static rtx | |
1384 | avoid_expensive_constant (enum machine_mode mode, optab binoptab, | |
68f932c4 | 1385 | int opn, rtx x, bool unsignedp) |
62442ab9 | 1386 | { |
c99102b8 | 1387 | bool speed = optimize_insn_for_speed_p (); |
fdb2c684 | 1388 | |
47de45c6 RS |
1389 | if (mode != VOIDmode |
1390 | && optimize | |
62442ab9 | 1391 | && CONSTANT_P (x) |
19b5fafb RH |
1392 | && (rtx_cost (x, optab_to_code (binoptab), opn, speed) |
1393 | > set_src_cost (x, speed))) | |
62442ab9 | 1394 | { |
481683e1 | 1395 | if (CONST_INT_P (x)) |
c722c7da RS |
1396 | { |
1397 | HOST_WIDE_INT intval = trunc_int_for_mode (INTVAL (x), mode); | |
1398 | if (intval != INTVAL (x)) | |
1399 | x = GEN_INT (intval); | |
1400 | } | |
1401 | else | |
62442ab9 RS |
1402 | x = convert_modes (mode, VOIDmode, x, unsignedp); |
1403 | x = force_reg (mode, x); | |
1404 | } | |
1405 | return x; | |
1406 | } | |
665d18c6 | 1407 | |
0aa222d1 SL |
1408 | /* Helper function for expand_binop: handle the case where there |
1409 | is an insn that directly implements the indicated operation. | |
1410 | Returns null if this is not possible. */ | |
1411 | static rtx | |
1412 | expand_binop_directly (enum machine_mode mode, optab binoptab, | |
1413 | rtx op0, rtx op1, | |
1414 | rtx target, int unsignedp, enum optab_methods methods, | |
62442ab9 | 1415 | rtx last) |
0aa222d1 | 1416 | { |
a484f6ba | 1417 | enum machine_mode from_mode = widened_mode (mode, op0, op1); |
5dfe80ba AS |
1418 | enum insn_code icode = find_widening_optab_handler (binoptab, mode, |
1419 | from_mode, 1); | |
4f431835 RS |
1420 | enum machine_mode xmode0 = insn_data[(int) icode].operand[1].mode; |
1421 | enum machine_mode xmode1 = insn_data[(int) icode].operand[2].mode; | |
1422 | enum machine_mode mode0, mode1, tmp_mode; | |
a5c7d693 | 1423 | struct expand_operand ops[3]; |
62442ab9 | 1424 | bool commutative_p; |
0aa222d1 SL |
1425 | rtx pat; |
1426 | rtx xop0 = op0, xop1 = op1; | |
62442ab9 | 1427 | rtx swap; |
b8698a0f | 1428 | |
0aa222d1 SL |
1429 | /* If it is a commutative operator and the modes would match |
1430 | if we would swap the operands, we can save the conversions. */ | |
62442ab9 RS |
1431 | commutative_p = commutative_optab_p (binoptab); |
1432 | if (commutative_p | |
4f431835 RS |
1433 | && GET_MODE (xop0) != xmode0 && GET_MODE (xop1) != xmode1 |
1434 | && GET_MODE (xop0) == xmode1 && GET_MODE (xop1) == xmode1) | |
0aa222d1 | 1435 | { |
62442ab9 RS |
1436 | swap = xop0; |
1437 | xop0 = xop1; | |
1438 | xop1 = swap; | |
0aa222d1 | 1439 | } |
b8698a0f | 1440 | |
62442ab9 | 1441 | /* If we are optimizing, force expensive constants into a register. */ |
68f932c4 | 1442 | xop0 = avoid_expensive_constant (xmode0, binoptab, 0, xop0, unsignedp); |
62442ab9 | 1443 | if (!shift_optab_p (binoptab)) |
68f932c4 | 1444 | xop1 = avoid_expensive_constant (xmode1, binoptab, 1, xop1, unsignedp); |
62442ab9 | 1445 | |
2b99b2b8 RS |
1446 | /* In case the insn wants input operands in modes different from |
1447 | those of the actual operands, convert the operands. It would | |
1448 | seem that we don't need to convert CONST_INTs, but we do, so | |
1449 | that they're properly zero-extended, sign-extended or truncated | |
1450 | for their mode. */ | |
1451 | ||
4f431835 RS |
1452 | mode0 = GET_MODE (xop0) != VOIDmode ? GET_MODE (xop0) : mode; |
1453 | if (xmode0 != VOIDmode && xmode0 != mode0) | |
1454 | { | |
1455 | xop0 = convert_modes (xmode0, mode0, xop0, unsignedp); | |
1456 | mode0 = xmode0; | |
1457 | } | |
1458 | ||
1459 | mode1 = GET_MODE (xop1) != VOIDmode ? GET_MODE (xop1) : mode; | |
1460 | if (xmode1 != VOIDmode && xmode1 != mode1) | |
1461 | { | |
1462 | xop1 = convert_modes (xmode1, mode1, xop1, unsignedp); | |
1463 | mode1 = xmode1; | |
1464 | } | |
2b99b2b8 RS |
1465 | |
1466 | /* If operation is commutative, | |
1467 | try to make the first operand a register. | |
1468 | Even better, try to make it the same as the target. | |
1469 | Also try to make the last operand a constant. */ | |
1470 | if (commutative_p | |
1471 | && swap_commutative_operands_with_target (target, xop0, xop1)) | |
1472 | { | |
1473 | swap = xop1; | |
1474 | xop1 = xop0; | |
1475 | xop0 = swap; | |
1476 | } | |
1477 | ||
0aa222d1 SL |
1478 | /* Now, if insn's predicates don't allow our operands, put them into |
1479 | pseudo regs. */ | |
b8698a0f | 1480 | |
b8698a0f | 1481 | if (binoptab == vec_pack_trunc_optab |
0aa222d1 SL |
1482 | || binoptab == vec_pack_usat_optab |
1483 | || binoptab == vec_pack_ssat_optab | |
1484 | || binoptab == vec_pack_ufix_trunc_optab | |
1485 | || binoptab == vec_pack_sfix_trunc_optab) | |
1486 | { | |
1487 | /* The mode of the result is different then the mode of the | |
1488 | arguments. */ | |
a5c7d693 | 1489 | tmp_mode = insn_data[(int) icode].operand[0].mode; |
0aa222d1 | 1490 | if (GET_MODE_NUNITS (tmp_mode) != 2 * GET_MODE_NUNITS (mode)) |
a5c7d693 RS |
1491 | { |
1492 | delete_insns_since (last); | |
1493 | return NULL_RTX; | |
1494 | } | |
0aa222d1 SL |
1495 | } |
1496 | else | |
1497 | tmp_mode = mode; | |
1498 | ||
a5c7d693 | 1499 | create_output_operand (&ops[0], target, tmp_mode); |
2b99b2b8 RS |
1500 | create_input_operand (&ops[1], xop0, mode0); |
1501 | create_input_operand (&ops[2], xop1, mode1); | |
1502 | pat = maybe_gen_insn (icode, 3, ops); | |
1503 | if (pat) | |
a5c7d693 | 1504 | { |
2b99b2b8 RS |
1505 | /* If PAT is composed of more than one insn, try to add an appropriate |
1506 | REG_EQUAL note to it. If we can't because TEMP conflicts with an | |
1507 | operand, call expand_binop again, this time without a target. */ | |
1508 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX | |
19b5fafb | 1509 | && ! add_equal_note (pat, ops[0].value, optab_to_code (binoptab), |
2b99b2b8 | 1510 | ops[1].value, ops[2].value)) |
0aa222d1 | 1511 | { |
2b99b2b8 RS |
1512 | delete_insns_since (last); |
1513 | return expand_binop (mode, binoptab, op0, op1, NULL_RTX, | |
1514 | unsignedp, methods); | |
0aa222d1 | 1515 | } |
b8698a0f | 1516 | |
2b99b2b8 RS |
1517 | emit_insn (pat); |
1518 | return ops[0].value; | |
a5c7d693 | 1519 | } |
0aa222d1 SL |
1520 | delete_insns_since (last); |
1521 | return NULL_RTX; | |
1522 | } | |
1523 | ||
77c9c6c2 RK |
1524 | /* Generate code to perform an operation specified by BINOPTAB |
1525 | on operands OP0 and OP1, with result having machine-mode MODE. | |
1526 | ||
1527 | UNSIGNEDP is for the case where we have to widen the operands | |
1528 | to perform the operation. It says to use zero-extension. | |
1529 | ||
1530 | If TARGET is nonzero, the value | |
1531 | is generated there, if it is convenient to do so. | |
1532 | In all cases an rtx is returned for the locus of the value; | |
1533 | this may or may not be TARGET. */ | |
1534 | ||
1535 | rtx | |
0c20a65f AJ |
1536 | expand_binop (enum machine_mode mode, optab binoptab, rtx op0, rtx op1, |
1537 | rtx target, int unsignedp, enum optab_methods methods) | |
77c9c6c2 | 1538 | { |
70864443 RK |
1539 | enum optab_methods next_methods |
1540 | = (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN | |
1541 | ? OPTAB_WIDEN : methods); | |
d858f359 | 1542 | enum mode_class mclass; |
77c9c6c2 | 1543 | enum machine_mode wider_mode; |
8a33f100 | 1544 | rtx libfunc; |
b3694847 | 1545 | rtx temp; |
abd418d3 | 1546 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
1547 | rtx last; |
1548 | ||
d858f359 | 1549 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 1550 | |
8aecce0a RK |
1551 | /* If subtracting an integer constant, convert this into an addition of |
1552 | the negated constant. */ | |
1553 | ||
481683e1 | 1554 | if (binoptab == sub_optab && CONST_INT_P (op1)) |
8aecce0a RK |
1555 | { |
1556 | op1 = negate_rtx (mode, op1); | |
1557 | binoptab = add_optab; | |
1558 | } | |
1559 | ||
77c9c6c2 RK |
1560 | /* Record where to delete back to if we backtrack. */ |
1561 | last = get_last_insn (); | |
1562 | ||
77c9c6c2 RK |
1563 | /* If we can do it with a three-operand insn, do so. */ |
1564 | ||
1565 | if (methods != OPTAB_MUST_WIDEN | |
5dfe80ba AS |
1566 | && find_widening_optab_handler (binoptab, mode, |
1567 | widened_mode (mode, op0, op1), 1) | |
a484f6ba | 1568 | != CODE_FOR_nothing) |
77c9c6c2 | 1569 | { |
0aa222d1 | 1570 | temp = expand_binop_directly (mode, binoptab, op0, op1, target, |
62442ab9 | 1571 | unsignedp, methods, last); |
0aa222d1 SL |
1572 | if (temp) |
1573 | return temp; | |
77c9c6c2 RK |
1574 | } |
1575 | ||
0aa222d1 SL |
1576 | /* If we were trying to rotate, and that didn't work, try rotating |
1577 | the other direction before falling back to shifts and bitwise-or. */ | |
1578 | if (((binoptab == rotl_optab | |
947131ba | 1579 | && optab_handler (rotr_optab, mode) != CODE_FOR_nothing) |
0aa222d1 | 1580 | || (binoptab == rotr_optab |
947131ba | 1581 | && optab_handler (rotl_optab, mode) != CODE_FOR_nothing)) |
d858f359 | 1582 | && mclass == MODE_INT) |
0f8594ee | 1583 | { |
0aa222d1 SL |
1584 | optab otheroptab = (binoptab == rotl_optab ? rotr_optab : rotl_optab); |
1585 | rtx newop1; | |
69660a70 | 1586 | unsigned int bits = GET_MODE_PRECISION (mode); |
0aa222d1 | 1587 | |
481683e1 | 1588 | if (CONST_INT_P (op1)) |
db826dae | 1589 | newop1 = GEN_INT (bits - INTVAL (op1)); |
0aa222d1 | 1590 | else if (targetm.shift_truncation_mask (mode) == bits - 1) |
db826dae | 1591 | newop1 = negate_rtx (GET_MODE (op1), op1); |
0aa222d1 | 1592 | else |
db826dae | 1593 | newop1 = expand_binop (GET_MODE (op1), sub_optab, |
2f1cd2eb | 1594 | gen_int_mode (bits, GET_MODE (op1)), op1, |
0aa222d1 | 1595 | NULL_RTX, unsignedp, OPTAB_DIRECT); |
b8698a0f | 1596 | |
0aa222d1 | 1597 | temp = expand_binop_directly (mode, otheroptab, op0, newop1, |
62442ab9 | 1598 | target, unsignedp, methods, last); |
0aa222d1 SL |
1599 | if (temp) |
1600 | return temp; | |
0f8594ee MM |
1601 | } |
1602 | ||
5a5064dc RK |
1603 | /* If this is a multiply, see if we can do a widening operation that |
1604 | takes operands of this mode and makes a wider mode. */ | |
1605 | ||
86556d87 | 1606 | if (binoptab == smul_optab |
0d44736e | 1607 | && GET_MODE_2XWIDER_MODE (mode) != VOIDmode |
a484f6ba AS |
1608 | && (widening_optab_handler ((unsignedp ? umul_widen_optab |
1609 | : smul_widen_optab), | |
1610 | GET_MODE_2XWIDER_MODE (mode), mode) | |
5a5064dc RK |
1611 | != CODE_FOR_nothing)) |
1612 | { | |
0d44736e | 1613 | temp = expand_binop (GET_MODE_2XWIDER_MODE (mode), |
5a5064dc | 1614 | unsignedp ? umul_widen_optab : smul_widen_optab, |
73d9a835 | 1615 | op0, op1, NULL_RTX, unsignedp, OPTAB_DIRECT); |
5a5064dc | 1616 | |
70864443 RK |
1617 | if (temp != 0) |
1618 | { | |
28f52a4d | 1619 | if (GET_MODE_CLASS (mode) == MODE_INT |
d0edd768 | 1620 | && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (temp))) |
70864443 RK |
1621 | return gen_lowpart (mode, temp); |
1622 | else | |
1623 | return convert_to_mode (mode, temp, unsignedp); | |
1624 | } | |
5a5064dc RK |
1625 | } |
1626 | ||
bdc3ee5d RH |
1627 | /* If this is a vector shift by a scalar, see if we can do a vector |
1628 | shift by a vector. If so, broadcast the scalar into a vector. */ | |
1629 | if (mclass == MODE_VECTOR_INT) | |
1630 | { | |
2225b9f2 | 1631 | optab otheroptab = unknown_optab; |
bdc3ee5d RH |
1632 | |
1633 | if (binoptab == ashl_optab) | |
1634 | otheroptab = vashl_optab; | |
1635 | else if (binoptab == ashr_optab) | |
1636 | otheroptab = vashr_optab; | |
1637 | else if (binoptab == lshr_optab) | |
1638 | otheroptab = vlshr_optab; | |
1639 | else if (binoptab == rotl_optab) | |
1640 | otheroptab = vrotl_optab; | |
1641 | else if (binoptab == rotr_optab) | |
1642 | otheroptab = vrotr_optab; | |
1643 | ||
1644 | if (otheroptab && optab_handler (otheroptab, mode) != CODE_FOR_nothing) | |
1645 | { | |
1646 | rtx vop1 = expand_vector_broadcast (mode, op1); | |
1647 | if (vop1) | |
1648 | { | |
1649 | temp = expand_binop_directly (mode, otheroptab, op0, vop1, | |
1650 | target, unsignedp, methods, last); | |
1651 | if (temp) | |
1652 | return temp; | |
1653 | } | |
1654 | } | |
1655 | } | |
1656 | ||
9a856ec7 | 1657 | /* Look for a wider mode of the same class for which we think we |
5a5064dc RK |
1658 | can open-code the operation. Check for a widening multiply at the |
1659 | wider mode as well. */ | |
9a856ec7 | 1660 | |
d858f359 | 1661 | if (CLASS_HAS_WIDER_MODES_P (mclass) |
6f43c157 | 1662 | && methods != OPTAB_DIRECT && methods != OPTAB_LIB) |
86556d87 BE |
1663 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
1664 | wider_mode != VOIDmode; | |
9a856ec7 RK |
1665 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
1666 | { | |
947131ba | 1667 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing |
5a5064dc RK |
1668 | || (binoptab == smul_optab |
1669 | && GET_MODE_WIDER_MODE (wider_mode) != VOIDmode | |
5dfe80ba AS |
1670 | && (find_widening_optab_handler ((unsignedp |
1671 | ? umul_widen_optab | |
1672 | : smul_widen_optab), | |
1673 | GET_MODE_WIDER_MODE (wider_mode), | |
1674 | mode, 0) | |
5a5064dc | 1675 | != CODE_FOR_nothing))) |
9a856ec7 RK |
1676 | { |
1677 | rtx xop0 = op0, xop1 = op1; | |
1678 | int no_extend = 0; | |
1679 | ||
1680 | /* For certain integer operations, we need not actually extend | |
1681 | the narrow operands, as long as we will truncate | |
6d2f8887 | 1682 | the results to the same narrowness. */ |
9a856ec7 RK |
1683 | |
1684 | if ((binoptab == ior_optab || binoptab == and_optab | |
1685 | || binoptab == xor_optab | |
1686 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 1687 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 1688 | && mclass == MODE_INT) |
62442ab9 RS |
1689 | { |
1690 | no_extend = 1; | |
68f932c4 | 1691 | xop0 = avoid_expensive_constant (mode, binoptab, 0, |
62442ab9 RS |
1692 | xop0, unsignedp); |
1693 | if (binoptab != ashl_optab) | |
68f932c4 | 1694 | xop1 = avoid_expensive_constant (mode, binoptab, 1, |
62442ab9 RS |
1695 | xop1, unsignedp); |
1696 | } | |
9a856ec7 | 1697 | |
0661a3de | 1698 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, no_extend); |
943cc242 RK |
1699 | |
1700 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 1701 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 1702 | no_extend && binoptab != ashl_optab); |
943cc242 | 1703 | |
b1ec3c92 | 1704 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
9a856ec7 RK |
1705 | unsignedp, OPTAB_DIRECT); |
1706 | if (temp) | |
1707 | { | |
d858f359 | 1708 | if (mclass != MODE_INT |
d0edd768 | 1709 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
9a856ec7 RK |
1710 | { |
1711 | if (target == 0) | |
1712 | target = gen_reg_rtx (mode); | |
1713 | convert_move (target, temp, 0); | |
1714 | return target; | |
1715 | } | |
1716 | else | |
1717 | return gen_lowpart (mode, temp); | |
1718 | } | |
1719 | else | |
1720 | delete_insns_since (last); | |
1721 | } | |
1722 | } | |
1723 | ||
62442ab9 RS |
1724 | /* If operation is commutative, |
1725 | try to make the first operand a register. | |
1726 | Even better, try to make it the same as the target. | |
1727 | Also try to make the last operand a constant. */ | |
1728 | if (commutative_optab_p (binoptab) | |
1729 | && swap_commutative_operands_with_target (target, op0, op1)) | |
1730 | { | |
1731 | temp = op1; | |
1732 | op1 = op0; | |
1733 | op0 = temp; | |
1734 | } | |
1735 | ||
77c9c6c2 RK |
1736 | /* These can be done a word at a time. */ |
1737 | if ((binoptab == and_optab || binoptab == ior_optab || binoptab == xor_optab) | |
d858f359 | 1738 | && mclass == MODE_INT |
77c9c6c2 | 1739 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 1740 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1741 | { |
bb93b973 | 1742 | int i; |
77c9c6c2 | 1743 | rtx insns; |
77c9c6c2 RK |
1744 | |
1745 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
1746 | won't be accurate, so use a new target. */ | |
02972eaf RS |
1747 | if (target == 0 |
1748 | || target == op0 | |
1749 | || target == op1 | |
1750 | || !valid_multiword_target_p (target)) | |
77c9c6c2 RK |
1751 | target = gen_reg_rtx (mode); |
1752 | ||
1753 | start_sequence (); | |
1754 | ||
1755 | /* Do the actual arithmetic. */ | |
1756 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
1757 | { | |
1758 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 1759 | rtx x = expand_binop (word_mode, binoptab, |
77c9c6c2 RK |
1760 | operand_subword_force (op0, i, mode), |
1761 | operand_subword_force (op1, i, mode), | |
70864443 RK |
1762 | target_piece, unsignedp, next_methods); |
1763 | ||
1764 | if (x == 0) | |
1765 | break; | |
1766 | ||
77c9c6c2 RK |
1767 | if (target_piece != x) |
1768 | emit_move_insn (target_piece, x); | |
1769 | } | |
1770 | ||
1771 | insns = get_insns (); | |
1772 | end_sequence (); | |
1773 | ||
70864443 RK |
1774 | if (i == GET_MODE_BITSIZE (mode) / BITS_PER_WORD) |
1775 | { | |
d70dcf29 | 1776 | emit_insn (insns); |
70864443 RK |
1777 | return target; |
1778 | } | |
77c9c6c2 RK |
1779 | } |
1780 | ||
8c597270 | 1781 | /* Synthesize double word shifts from single word shifts. */ |
e5df894b RK |
1782 | if ((binoptab == lshr_optab || binoptab == ashl_optab |
1783 | || binoptab == ashr_optab) | |
d858f359 | 1784 | && mclass == MODE_INT |
481683e1 | 1785 | && (CONST_INT_P (op1) || optimize_insn_for_speed_p ()) |
8c597270 | 1786 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
0d44736e | 1787 | && GET_MODE_PRECISION (mode) == GET_MODE_BITSIZE (mode) |
947131ba RS |
1788 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing |
1789 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing | |
1790 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1791 | { |
273a2526 RS |
1792 | unsigned HOST_WIDE_INT shift_mask, double_shift_mask; |
1793 | enum machine_mode op1_mode; | |
8c597270 | 1794 | |
273a2526 RS |
1795 | double_shift_mask = targetm.shift_truncation_mask (mode); |
1796 | shift_mask = targetm.shift_truncation_mask (word_mode); | |
1797 | op1_mode = GET_MODE (op1) != VOIDmode ? GET_MODE (op1) : word_mode; | |
8c597270 | 1798 | |
273a2526 | 1799 | /* Apply the truncation to constant shifts. */ |
481683e1 | 1800 | if (double_shift_mask > 0 && CONST_INT_P (op1)) |
273a2526 | 1801 | op1 = GEN_INT (INTVAL (op1) & double_shift_mask); |
8c597270 | 1802 | |
273a2526 RS |
1803 | if (op1 == CONST0_RTX (op1_mode)) |
1804 | return op0; | |
8c597270 | 1805 | |
273a2526 RS |
1806 | /* Make sure that this is a combination that expand_doubleword_shift |
1807 | can handle. See the comments there for details. */ | |
1808 | if (double_shift_mask == 0 | |
1809 | || (shift_mask == BITS_PER_WORD - 1 | |
1810 | && double_shift_mask == BITS_PER_WORD * 2 - 1)) | |
8c597270 | 1811 | { |
d70dcf29 | 1812 | rtx insns; |
273a2526 RS |
1813 | rtx into_target, outof_target; |
1814 | rtx into_input, outof_input; | |
1815 | int left_shift, outof_word; | |
8c597270 | 1816 | |
273a2526 RS |
1817 | /* If TARGET is the same as one of the operands, the REG_EQUAL note |
1818 | won't be accurate, so use a new target. */ | |
02972eaf RS |
1819 | if (target == 0 |
1820 | || target == op0 | |
1821 | || target == op1 | |
1822 | || !valid_multiword_target_p (target)) | |
273a2526 | 1823 | target = gen_reg_rtx (mode); |
8c597270 | 1824 | |
273a2526 | 1825 | start_sequence (); |
8c597270 | 1826 | |
273a2526 RS |
1827 | /* OUTOF_* is the word we are shifting bits away from, and |
1828 | INTO_* is the word that we are shifting bits towards, thus | |
1829 | they differ depending on the direction of the shift and | |
1830 | WORDS_BIG_ENDIAN. */ | |
70864443 | 1831 | |
273a2526 RS |
1832 | left_shift = binoptab == ashl_optab; |
1833 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
70864443 | 1834 | |
273a2526 RS |
1835 | outof_target = operand_subword (target, outof_word, 1, mode); |
1836 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
cf2f7113 | 1837 | |
273a2526 RS |
1838 | outof_input = operand_subword_force (op0, outof_word, mode); |
1839 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
0c20a65f | 1840 | |
273a2526 RS |
1841 | if (expand_doubleword_shift (op1_mode, binoptab, |
1842 | outof_input, into_input, op1, | |
1843 | outof_target, into_target, | |
f8bdb931 | 1844 | unsignedp, next_methods, shift_mask)) |
273a2526 RS |
1845 | { |
1846 | insns = get_insns (); | |
1847 | end_sequence (); | |
8c597270 | 1848 | |
d70dcf29 | 1849 | emit_insn (insns); |
273a2526 RS |
1850 | return target; |
1851 | } | |
1852 | end_sequence (); | |
70864443 | 1853 | } |
8c597270 JW |
1854 | } |
1855 | ||
1856 | /* Synthesize double word rotates from single word shifts. */ | |
1857 | if ((binoptab == rotl_optab || binoptab == rotr_optab) | |
d858f359 | 1858 | && mclass == MODE_INT |
481683e1 | 1859 | && CONST_INT_P (op1) |
0d44736e | 1860 | && GET_MODE_PRECISION (mode) == 2 * BITS_PER_WORD |
947131ba RS |
1861 | && optab_handler (ashl_optab, word_mode) != CODE_FOR_nothing |
1862 | && optab_handler (lshr_optab, word_mode) != CODE_FOR_nothing) | |
8c597270 | 1863 | { |
ebd8b60d | 1864 | rtx insns; |
8c597270 JW |
1865 | rtx into_target, outof_target; |
1866 | rtx into_input, outof_input; | |
70864443 | 1867 | rtx inter; |
8c597270 JW |
1868 | int shift_count, left_shift, outof_word; |
1869 | ||
1870 | /* If TARGET is the same as one of the operands, the REG_EQUAL note | |
0c0ab0f1 OH |
1871 | won't be accurate, so use a new target. Do this also if target is not |
1872 | a REG, first because having a register instead may open optimization | |
1ae58c30 | 1873 | opportunities, and second because if target and op0 happen to be MEMs |
0c0ab0f1 OH |
1874 | designating the same location, we would risk clobbering it too early |
1875 | in the code sequence we generate below. */ | |
02972eaf RS |
1876 | if (target == 0 |
1877 | || target == op0 | |
1878 | || target == op1 | |
1879 | || !REG_P (target) | |
1880 | || !valid_multiword_target_p (target)) | |
8c597270 JW |
1881 | target = gen_reg_rtx (mode); |
1882 | ||
1883 | start_sequence (); | |
1884 | ||
1885 | shift_count = INTVAL (op1); | |
1886 | ||
1887 | /* OUTOF_* is the word we are shifting bits away from, and | |
1888 | INTO_* is the word that we are shifting bits towards, thus | |
1889 | they differ depending on the direction of the shift and | |
1890 | WORDS_BIG_ENDIAN. */ | |
1891 | ||
1892 | left_shift = (binoptab == rotl_optab); | |
1893 | outof_word = left_shift ^ ! WORDS_BIG_ENDIAN; | |
1894 | ||
1895 | outof_target = operand_subword (target, outof_word, 1, mode); | |
1896 | into_target = operand_subword (target, 1 - outof_word, 1, mode); | |
1897 | ||
1898 | outof_input = operand_subword_force (op0, outof_word, mode); | |
1899 | into_input = operand_subword_force (op0, 1 - outof_word, mode); | |
1900 | ||
1901 | if (shift_count == BITS_PER_WORD) | |
1902 | { | |
1903 | /* This is just a word swap. */ | |
1904 | emit_move_insn (outof_target, into_input); | |
1905 | emit_move_insn (into_target, outof_input); | |
70864443 | 1906 | inter = const0_rtx; |
8c597270 JW |
1907 | } |
1908 | else | |
1909 | { | |
1910 | rtx into_temp1, into_temp2, outof_temp1, outof_temp2; | |
1911 | rtx first_shift_count, second_shift_count; | |
1912 | optab reverse_unsigned_shift, unsigned_shift; | |
1913 | ||
1914 | reverse_unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1915 | ? lshr_optab : ashl_optab); | |
1916 | ||
1917 | unsigned_shift = (left_shift ^ (shift_count < BITS_PER_WORD) | |
1918 | ? ashl_optab : lshr_optab); | |
1919 | ||
1920 | if (shift_count > BITS_PER_WORD) | |
1921 | { | |
1922 | first_shift_count = GEN_INT (shift_count - BITS_PER_WORD); | |
7e1a450d | 1923 | second_shift_count = GEN_INT (2 * BITS_PER_WORD - shift_count); |
8c597270 JW |
1924 | } |
1925 | else | |
1926 | { | |
1927 | first_shift_count = GEN_INT (BITS_PER_WORD - shift_count); | |
1928 | second_shift_count = GEN_INT (shift_count); | |
1929 | } | |
1930 | ||
1931 | into_temp1 = expand_binop (word_mode, unsigned_shift, | |
1932 | outof_input, first_shift_count, | |
70864443 | 1933 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1934 | into_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1935 | into_input, second_shift_count, | |
5be5c8d4 | 1936 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1937 | |
1938 | if (into_temp1 != 0 && into_temp2 != 0) | |
1939 | inter = expand_binop (word_mode, ior_optab, into_temp1, into_temp2, | |
1940 | into_target, unsignedp, next_methods); | |
1941 | else | |
1942 | inter = 0; | |
1943 | ||
cb5b00cf | 1944 | if (inter != 0 && inter != into_target) |
70864443 | 1945 | emit_move_insn (into_target, inter); |
8c597270 JW |
1946 | |
1947 | outof_temp1 = expand_binop (word_mode, unsigned_shift, | |
1948 | into_input, first_shift_count, | |
70864443 | 1949 | NULL_RTX, unsignedp, next_methods); |
8c597270 JW |
1950 | outof_temp2 = expand_binop (word_mode, reverse_unsigned_shift, |
1951 | outof_input, second_shift_count, | |
5be5c8d4 | 1952 | NULL_RTX, unsignedp, next_methods); |
70864443 RK |
1953 | |
1954 | if (inter != 0 && outof_temp1 != 0 && outof_temp2 != 0) | |
1955 | inter = expand_binop (word_mode, ior_optab, | |
1956 | outof_temp1, outof_temp2, | |
1957 | outof_target, unsignedp, next_methods); | |
1958 | ||
cb5b00cf | 1959 | if (inter != 0 && inter != outof_target) |
70864443 | 1960 | emit_move_insn (outof_target, inter); |
8c597270 JW |
1961 | } |
1962 | ||
1963 | insns = get_insns (); | |
1964 | end_sequence (); | |
1965 | ||
70864443 RK |
1966 | if (inter != 0) |
1967 | { | |
ebd8b60d | 1968 | emit_insn (insns); |
70864443 RK |
1969 | return target; |
1970 | } | |
8c597270 JW |
1971 | } |
1972 | ||
77c9c6c2 RK |
1973 | /* These can be done a word at a time by propagating carries. */ |
1974 | if ((binoptab == add_optab || binoptab == sub_optab) | |
d858f359 | 1975 | && mclass == MODE_INT |
77c9c6c2 | 1976 | && GET_MODE_SIZE (mode) >= 2 * UNITS_PER_WORD |
947131ba | 1977 | && optab_handler (binoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 1978 | { |
e2500fed | 1979 | unsigned int i; |
77c9c6c2 | 1980 | optab otheroptab = binoptab == add_optab ? sub_optab : add_optab; |
a4b5414c | 1981 | const unsigned int nwords = GET_MODE_BITSIZE (mode) / BITS_PER_WORD; |
07444f1d | 1982 | rtx carry_in = NULL_RTX, carry_out = NULL_RTX; |
64de6c0a | 1983 | rtx xop0, xop1, xtarget; |
77c9c6c2 RK |
1984 | |
1985 | /* We can handle either a 1 or -1 value for the carry. If STORE_FLAG | |
1986 | value is one of those, use it. Otherwise, use 1 since it is the | |
1987 | one easiest to get. */ | |
1988 | #if STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1 | |
1989 | int normalizep = STORE_FLAG_VALUE; | |
1990 | #else | |
1991 | int normalizep = 1; | |
1992 | #endif | |
1993 | ||
1994 | /* Prepare the operands. */ | |
cee85023 RS |
1995 | xop0 = force_reg (mode, op0); |
1996 | xop1 = force_reg (mode, op1); | |
77c9c6c2 | 1997 | |
64de6c0a DE |
1998 | xtarget = gen_reg_rtx (mode); |
1999 | ||
02972eaf | 2000 | if (target == 0 || !REG_P (target) || !valid_multiword_target_p (target)) |
64de6c0a | 2001 | target = xtarget; |
77c9c6c2 | 2002 | |
af2cc4dd | 2003 | /* Indicate for flow that the entire target reg is being set. */ |
f8cfc6aa | 2004 | if (REG_P (target)) |
c41c1387 | 2005 | emit_clobber (xtarget); |
af2cc4dd | 2006 | |
77c9c6c2 RK |
2007 | /* Do the actual arithmetic. */ |
2008 | for (i = 0; i < nwords; i++) | |
2009 | { | |
2010 | int index = (WORDS_BIG_ENDIAN ? nwords - i - 1 : i); | |
64de6c0a | 2011 | rtx target_piece = operand_subword (xtarget, index, 1, mode); |
cee85023 RS |
2012 | rtx op0_piece = operand_subword_force (xop0, index, mode); |
2013 | rtx op1_piece = operand_subword_force (xop1, index, mode); | |
77c9c6c2 RK |
2014 | rtx x; |
2015 | ||
2016 | /* Main add/subtract of the input operands. */ | |
34e56753 | 2017 | x = expand_binop (word_mode, binoptab, |
77c9c6c2 | 2018 | op0_piece, op1_piece, |
70864443 | 2019 | target_piece, unsignedp, next_methods); |
77c9c6c2 RK |
2020 | if (x == 0) |
2021 | break; | |
2022 | ||
2023 | if (i + 1 < nwords) | |
2024 | { | |
2025 | /* Store carry from main add/subtract. */ | |
34e56753 | 2026 | carry_out = gen_reg_rtx (word_mode); |
23357404 TG |
2027 | carry_out = emit_store_flag_force (carry_out, |
2028 | (binoptab == add_optab | |
b30f05db | 2029 | ? LT : GT), |
23357404 TG |
2030 | x, op0_piece, |
2031 | word_mode, 1, normalizep); | |
77c9c6c2 RK |
2032 | } |
2033 | ||
2034 | if (i > 0) | |
2035 | { | |
859cb4d8 | 2036 | rtx newx; |
0c20a65f | 2037 | |
77c9c6c2 | 2038 | /* Add/subtract previous carry to main result. */ |
859cb4d8 GK |
2039 | newx = expand_binop (word_mode, |
2040 | normalizep == 1 ? binoptab : otheroptab, | |
2041 | x, carry_in, | |
2042 | NULL_RTX, 1, next_methods); | |
77c9c6c2 RK |
2043 | |
2044 | if (i + 1 < nwords) | |
2045 | { | |
77c9c6c2 | 2046 | /* Get out carry from adding/subtracting carry in. */ |
859cb4d8 | 2047 | rtx carry_tmp = gen_reg_rtx (word_mode); |
23357404 | 2048 | carry_tmp = emit_store_flag_force (carry_tmp, |
859cb4d8 GK |
2049 | (binoptab == add_optab |
2050 | ? LT : GT), | |
2051 | newx, x, | |
23357404 | 2052 | word_mode, 1, normalizep); |
70864443 | 2053 | |
77c9c6c2 | 2054 | /* Logical-ior the two poss. carry together. */ |
34e56753 | 2055 | carry_out = expand_binop (word_mode, ior_optab, |
77c9c6c2 | 2056 | carry_out, carry_tmp, |
70864443 RK |
2057 | carry_out, 0, next_methods); |
2058 | if (carry_out == 0) | |
77c9c6c2 RK |
2059 | break; |
2060 | } | |
859cb4d8 | 2061 | emit_move_insn (target_piece, newx); |
77c9c6c2 | 2062 | } |
06cd9d72 DD |
2063 | else |
2064 | { | |
2065 | if (x != target_piece) | |
2066 | emit_move_insn (target_piece, x); | |
2067 | } | |
77c9c6c2 RK |
2068 | |
2069 | carry_in = carry_out; | |
0c20a65f | 2070 | } |
77c9c6c2 | 2071 | |
e2500fed | 2072 | if (i == GET_MODE_BITSIZE (mode) / (unsigned) BITS_PER_WORD) |
77c9c6c2 | 2073 | { |
947131ba | 2074 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing |
d0ccc658 | 2075 | || ! rtx_equal_p (target, xtarget)) |
02214a5c | 2076 | { |
64de6c0a | 2077 | rtx temp = emit_move_insn (target, xtarget); |
70864443 | 2078 | |
7543f918 | 2079 | set_dst_reg_note (temp, REG_EQUAL, |
19b5fafb RH |
2080 | gen_rtx_fmt_ee (optab_to_code (binoptab), |
2081 | mode, copy_rtx (xop0), | |
7543f918 JR |
2082 | copy_rtx (xop1)), |
2083 | target); | |
02214a5c | 2084 | } |
2cd622c3 AO |
2085 | else |
2086 | target = xtarget; | |
c5c76735 | 2087 | |
77c9c6c2 RK |
2088 | return target; |
2089 | } | |
c5c76735 | 2090 | |
77c9c6c2 RK |
2091 | else |
2092 | delete_insns_since (last); | |
2093 | } | |
2094 | ||
f927760b RS |
2095 | /* Attempt to synthesize double word multiplies using a sequence of word |
2096 | mode multiplications. We first attempt to generate a sequence using a | |
2097 | more efficient unsigned widening multiply, and if that fails we then | |
2098 | try using a signed widening multiply. */ | |
77c9c6c2 RK |
2099 | |
2100 | if (binoptab == smul_optab | |
d858f359 | 2101 | && mclass == MODE_INT |
77c9c6c2 | 2102 | && GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD |
947131ba RS |
2103 | && optab_handler (smul_optab, word_mode) != CODE_FOR_nothing |
2104 | && optab_handler (add_optab, word_mode) != CODE_FOR_nothing) | |
77c9c6c2 | 2105 | { |
f927760b | 2106 | rtx product = NULL_RTX; |
a484f6ba AS |
2107 | if (widening_optab_handler (umul_widen_optab, mode, word_mode) |
2108 | != CODE_FOR_nothing) | |
f927760b RS |
2109 | { |
2110 | product = expand_doubleword_mult (mode, op0, op1, target, | |
2111 | true, methods); | |
2112 | if (!product) | |
77c9c6c2 | 2113 | delete_insns_since (last); |
77c9c6c2 RK |
2114 | } |
2115 | ||
f927760b | 2116 | if (product == NULL_RTX |
a484f6ba AS |
2117 | && widening_optab_handler (smul_widen_optab, mode, word_mode) |
2118 | != CODE_FOR_nothing) | |
77c9c6c2 | 2119 | { |
f927760b RS |
2120 | product = expand_doubleword_mult (mode, op0, op1, target, |
2121 | false, methods); | |
2122 | if (!product) | |
2123 | delete_insns_since (last); | |
77c9c6c2 RK |
2124 | } |
2125 | ||
f927760b | 2126 | if (product != NULL_RTX) |
77c9c6c2 | 2127 | { |
947131ba | 2128 | if (optab_handler (mov_optab, mode) != CODE_FOR_nothing) |
70864443 | 2129 | { |
f927760b | 2130 | temp = emit_move_insn (target ? target : product, product); |
7543f918 JR |
2131 | set_dst_reg_note (temp, |
2132 | REG_EQUAL, | |
2133 | gen_rtx_fmt_ee (MULT, mode, | |
2134 | copy_rtx (op0), | |
2135 | copy_rtx (op1)), | |
2136 | target ? target : product); | |
77c9c6c2 | 2137 | } |
f927760b | 2138 | return product; |
77c9c6c2 | 2139 | } |
77c9c6c2 RK |
2140 | } |
2141 | ||
2142 | /* It can't be open-coded in this mode. | |
2143 | Use a library call if one is available and caller says that's ok. */ | |
2144 | ||
8a33f100 JH |
2145 | libfunc = optab_libfunc (binoptab, mode); |
2146 | if (libfunc | |
77c9c6c2 RK |
2147 | && (methods == OPTAB_LIB || methods == OPTAB_LIB_WIDEN)) |
2148 | { | |
2149 | rtx insns; | |
0bbb7f4d RS |
2150 | rtx op1x = op1; |
2151 | enum machine_mode op1_mode = mode; | |
9a7f678c | 2152 | rtx value; |
77c9c6c2 RK |
2153 | |
2154 | start_sequence (); | |
2155 | ||
62442ab9 | 2156 | if (shift_optab_p (binoptab)) |
0bbb7f4d | 2157 | { |
c7ff6e7a | 2158 | op1_mode = targetm.libgcc_shift_count_mode (); |
0bbb7f4d RS |
2159 | /* Specify unsigned here, |
2160 | since negative shift counts are meaningless. */ | |
c7ff6e7a | 2161 | op1x = convert_to_mode (op1_mode, op1, 1); |
0bbb7f4d RS |
2162 | } |
2163 | ||
82f0e2cc RK |
2164 | if (GET_MODE (op0) != VOIDmode |
2165 | && GET_MODE (op0) != mode) | |
5035bbfe TG |
2166 | op0 = convert_to_mode (mode, op0, unsignedp); |
2167 | ||
77c9c6c2 RK |
2168 | /* Pass 1 for NO_QUEUE so we don't lose any increments |
2169 | if the libcall is cse'd or moved. */ | |
8a33f100 | 2170 | value = emit_library_call_value (libfunc, |
ebb1b59a | 2171 | NULL_RTX, LCT_CONST, mode, 2, |
9a7f678c | 2172 | op0, mode, op1x, op1_mode); |
77c9c6c2 RK |
2173 | |
2174 | insns = get_insns (); | |
2175 | end_sequence (); | |
2176 | ||
2177 | target = gen_reg_rtx (mode); | |
b55f62cc | 2178 | emit_libcall_block_1 (insns, target, value, |
19b5fafb RH |
2179 | gen_rtx_fmt_ee (optab_to_code (binoptab), |
2180 | mode, op0, op1), | |
b55f62cc | 2181 | trapv_binoptab_p (binoptab)); |
77c9c6c2 RK |
2182 | |
2183 | return target; | |
2184 | } | |
2185 | ||
2186 | delete_insns_since (last); | |
2187 | ||
2188 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2189 | ||
2190 | if (! (methods == OPTAB_WIDEN || methods == OPTAB_LIB_WIDEN | |
2191 | || methods == OPTAB_MUST_WIDEN)) | |
abd418d3 RS |
2192 | { |
2193 | /* Caller says, don't even try. */ | |
2194 | delete_insns_since (entry_last); | |
2195 | return 0; | |
2196 | } | |
77c9c6c2 RK |
2197 | |
2198 | /* Compute the value of METHODS to pass to recursive calls. | |
2199 | Don't allow widening to be tried recursively. */ | |
2200 | ||
2201 | methods = (methods == OPTAB_LIB_WIDEN ? OPTAB_LIB : OPTAB_DIRECT); | |
2202 | ||
34e56753 RS |
2203 | /* Look for a wider mode of the same class for which it appears we can do |
2204 | the operation. */ | |
77c9c6c2 | 2205 | |
d858f359 | 2206 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 2207 | { |
86556d87 BE |
2208 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2209 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2210 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2211 | { | |
5dfe80ba | 2212 | if (find_widening_optab_handler (binoptab, wider_mode, mode, 1) |
a484f6ba | 2213 | != CODE_FOR_nothing |
77c9c6c2 | 2214 | || (methods == OPTAB_LIB |
8a33f100 | 2215 | && optab_libfunc (binoptab, wider_mode))) |
77c9c6c2 RK |
2216 | { |
2217 | rtx xop0 = op0, xop1 = op1; | |
2218 | int no_extend = 0; | |
2219 | ||
34e56753 | 2220 | /* For certain integer operations, we need not actually extend |
77c9c6c2 | 2221 | the narrow operands, as long as we will truncate |
835532b8 | 2222 | the results to the same narrowness. */ |
77c9c6c2 | 2223 | |
34e56753 RS |
2224 | if ((binoptab == ior_optab || binoptab == and_optab |
2225 | || binoptab == xor_optab | |
2226 | || binoptab == add_optab || binoptab == sub_optab | |
e5df894b | 2227 | || binoptab == smul_optab || binoptab == ashl_optab) |
d858f359 | 2228 | && mclass == MODE_INT) |
77c9c6c2 RK |
2229 | no_extend = 1; |
2230 | ||
0661a3de RS |
2231 | xop0 = widen_operand (xop0, wider_mode, mode, |
2232 | unsignedp, no_extend); | |
943cc242 RK |
2233 | |
2234 | /* The second operand of a shift must always be extended. */ | |
0661a3de | 2235 | xop1 = widen_operand (xop1, wider_mode, mode, unsignedp, |
e5df894b | 2236 | no_extend && binoptab != ashl_optab); |
77c9c6c2 | 2237 | |
b1ec3c92 | 2238 | temp = expand_binop (wider_mode, binoptab, xop0, xop1, NULL_RTX, |
77c9c6c2 RK |
2239 | unsignedp, methods); |
2240 | if (temp) | |
2241 | { | |
d858f359 | 2242 | if (mclass != MODE_INT |
d0edd768 | 2243 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
77c9c6c2 RK |
2244 | { |
2245 | if (target == 0) | |
2246 | target = gen_reg_rtx (mode); | |
2247 | convert_move (target, temp, 0); | |
2248 | return target; | |
2249 | } | |
2250 | else | |
2251 | return gen_lowpart (mode, temp); | |
2252 | } | |
2253 | else | |
2254 | delete_insns_since (last); | |
2255 | } | |
2256 | } | |
2257 | } | |
2258 | ||
abd418d3 | 2259 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2260 | return 0; |
2261 | } | |
2262 | \f | |
2263 | /* Expand a binary operator which has both signed and unsigned forms. | |
2264 | UOPTAB is the optab for unsigned operations, and SOPTAB is for | |
2265 | signed operations. | |
2266 | ||
2267 | If we widen unsigned operands, we may use a signed wider operation instead | |
2268 | of an unsigned wider operation, since the result would be the same. */ | |
2269 | ||
2270 | rtx | |
0c20a65f AJ |
2271 | sign_expand_binop (enum machine_mode mode, optab uoptab, optab soptab, |
2272 | rtx op0, rtx op1, rtx target, int unsignedp, | |
2273 | enum optab_methods methods) | |
77c9c6c2 | 2274 | { |
b3694847 | 2275 | rtx temp; |
77c9c6c2 | 2276 | optab direct_optab = unsignedp ? uoptab : soptab; |
cd1440b1 | 2277 | bool save_enable; |
77c9c6c2 RK |
2278 | |
2279 | /* Do it without widening, if possible. */ | |
2280 | temp = expand_binop (mode, direct_optab, op0, op1, target, | |
2281 | unsignedp, OPTAB_DIRECT); | |
2282 | if (temp || methods == OPTAB_DIRECT) | |
2283 | return temp; | |
2284 | ||
cd1440b1 RH |
2285 | /* Try widening to a signed int. Disable any direct use of any |
2286 | signed insn in the current mode. */ | |
2287 | save_enable = swap_optab_enable (soptab, mode, false); | |
77c9c6c2 | 2288 | |
cd1440b1 | 2289 | temp = expand_binop (mode, soptab, op0, op1, target, |
77c9c6c2 RK |
2290 | unsignedp, OPTAB_WIDEN); |
2291 | ||
2292 | /* For unsigned operands, try widening to an unsigned int. */ | |
cd1440b1 | 2293 | if (!temp && unsignedp) |
77c9c6c2 RK |
2294 | temp = expand_binop (mode, uoptab, op0, op1, target, |
2295 | unsignedp, OPTAB_WIDEN); | |
2296 | if (temp || methods == OPTAB_WIDEN) | |
cd1440b1 | 2297 | goto egress; |
77c9c6c2 | 2298 | |
f90b7a5a | 2299 | /* Use the right width libcall if that exists. */ |
cd1440b1 RH |
2300 | temp = expand_binop (mode, direct_optab, op0, op1, target, |
2301 | unsignedp, OPTAB_LIB); | |
77c9c6c2 | 2302 | if (temp || methods == OPTAB_LIB) |
cd1440b1 | 2303 | goto egress; |
77c9c6c2 | 2304 | |
f90b7a5a | 2305 | /* Must widen and use a libcall, use either signed or unsigned. */ |
cd1440b1 | 2306 | temp = expand_binop (mode, soptab, op0, op1, target, |
77c9c6c2 | 2307 | unsignedp, methods); |
cd1440b1 RH |
2308 | if (!temp && unsignedp) |
2309 | temp = expand_binop (mode, uoptab, op0, op1, target, | |
77c9c6c2 | 2310 | unsignedp, methods); |
cd1440b1 RH |
2311 | |
2312 | egress: | |
2313 | /* Undo the fiddling above. */ | |
2314 | if (save_enable) | |
2315 | swap_optab_enable (soptab, mode, true); | |
2316 | return temp; | |
77c9c6c2 RK |
2317 | } |
2318 | \f | |
6c7cf1f0 UB |
2319 | /* Generate code to perform an operation specified by UNOPPTAB |
2320 | on operand OP0, with two results to TARG0 and TARG1. | |
2321 | We assume that the order of the operands for the instruction | |
2322 | is TARG0, TARG1, OP0. | |
2323 | ||
2324 | Either TARG0 or TARG1 may be zero, but what that means is that | |
2325 | the result is not actually wanted. We will generate it into | |
2326 | a dummy pseudo-reg and discard it. They may not both be zero. | |
2327 | ||
2328 | Returns 1 if this operation can be performed; 0 if not. */ | |
2329 | ||
2330 | int | |
a072d43b | 2331 | expand_twoval_unop (optab unoptab, rtx op0, rtx targ0, rtx targ1, |
6c7cf1f0 UB |
2332 | int unsignedp) |
2333 | { | |
2334 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2335 | enum mode_class mclass; |
6c7cf1f0 UB |
2336 | enum machine_mode wider_mode; |
2337 | rtx entry_last = get_last_insn (); | |
2338 | rtx last; | |
2339 | ||
d858f359 | 2340 | mclass = GET_MODE_CLASS (mode); |
6c7cf1f0 | 2341 | |
ad76cef8 | 2342 | if (!targ0) |
6c7cf1f0 | 2343 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2344 | if (!targ1) |
6c7cf1f0 UB |
2345 | targ1 = gen_reg_rtx (mode); |
2346 | ||
2347 | /* Record where to go back to if we fail. */ | |
2348 | last = get_last_insn (); | |
2349 | ||
947131ba | 2350 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
6c7cf1f0 | 2351 | { |
a5c7d693 RS |
2352 | struct expand_operand ops[3]; |
2353 | enum insn_code icode = optab_handler (unoptab, mode); | |
6c7cf1f0 | 2354 | |
a5c7d693 RS |
2355 | create_fixed_operand (&ops[0], targ0); |
2356 | create_fixed_operand (&ops[1], targ1); | |
2357 | create_convert_operand_from (&ops[2], op0, mode, unsignedp); | |
2358 | if (maybe_expand_insn (icode, 3, ops)) | |
2359 | return 1; | |
6c7cf1f0 UB |
2360 | } |
2361 | ||
2362 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2363 | ||
d858f359 | 2364 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
6c7cf1f0 | 2365 | { |
86556d87 BE |
2366 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2367 | wider_mode != VOIDmode; | |
6c7cf1f0 UB |
2368 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2369 | { | |
947131ba | 2370 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
6c7cf1f0 UB |
2371 | { |
2372 | rtx t0 = gen_reg_rtx (wider_mode); | |
2373 | rtx t1 = gen_reg_rtx (wider_mode); | |
2374 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); | |
2375 | ||
a072d43b | 2376 | if (expand_twoval_unop (unoptab, cop0, t0, t1, unsignedp)) |
6c7cf1f0 UB |
2377 | { |
2378 | convert_move (targ0, t0, unsignedp); | |
2379 | convert_move (targ1, t1, unsignedp); | |
2380 | return 1; | |
2381 | } | |
2382 | else | |
2383 | delete_insns_since (last); | |
2384 | } | |
2385 | } | |
2386 | } | |
2387 | ||
2388 | delete_insns_since (entry_last); | |
2389 | return 0; | |
2390 | } | |
2391 | \f | |
77c9c6c2 RK |
2392 | /* Generate code to perform an operation specified by BINOPTAB |
2393 | on operands OP0 and OP1, with two results to TARG1 and TARG2. | |
2394 | We assume that the order of the operands for the instruction | |
2395 | is TARG0, OP0, OP1, TARG1, which would fit a pattern like | |
2396 | [(set TARG0 (operate OP0 OP1)) (set TARG1 (operate ...))]. | |
2397 | ||
2398 | Either TARG0 or TARG1 may be zero, but what that means is that | |
38e01259 | 2399 | the result is not actually wanted. We will generate it into |
77c9c6c2 RK |
2400 | a dummy pseudo-reg and discard it. They may not both be zero. |
2401 | ||
2402 | Returns 1 if this operation can be performed; 0 if not. */ | |
2403 | ||
2404 | int | |
0c20a65f AJ |
2405 | expand_twoval_binop (optab binoptab, rtx op0, rtx op1, rtx targ0, rtx targ1, |
2406 | int unsignedp) | |
77c9c6c2 RK |
2407 | { |
2408 | enum machine_mode mode = GET_MODE (targ0 ? targ0 : targ1); | |
d858f359 | 2409 | enum mode_class mclass; |
77c9c6c2 | 2410 | enum machine_mode wider_mode; |
abd418d3 | 2411 | rtx entry_last = get_last_insn (); |
77c9c6c2 RK |
2412 | rtx last; |
2413 | ||
d858f359 | 2414 | mclass = GET_MODE_CLASS (mode); |
77c9c6c2 | 2415 | |
ad76cef8 | 2416 | if (!targ0) |
77c9c6c2 | 2417 | targ0 = gen_reg_rtx (mode); |
ad76cef8 | 2418 | if (!targ1) |
77c9c6c2 RK |
2419 | targ1 = gen_reg_rtx (mode); |
2420 | ||
2421 | /* Record where to go back to if we fail. */ | |
2422 | last = get_last_insn (); | |
2423 | ||
947131ba | 2424 | if (optab_handler (binoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 2425 | { |
a5c7d693 RS |
2426 | struct expand_operand ops[4]; |
2427 | enum insn_code icode = optab_handler (binoptab, mode); | |
a995e389 RH |
2428 | enum machine_mode mode0 = insn_data[icode].operand[1].mode; |
2429 | enum machine_mode mode1 = insn_data[icode].operand[2].mode; | |
77c9c6c2 RK |
2430 | rtx xop0 = op0, xop1 = op1; |
2431 | ||
62442ab9 | 2432 | /* If we are optimizing, force expensive constants into a register. */ |
68f932c4 RS |
2433 | xop0 = avoid_expensive_constant (mode0, binoptab, 0, xop0, unsignedp); |
2434 | xop1 = avoid_expensive_constant (mode1, binoptab, 1, xop1, unsignedp); | |
62442ab9 | 2435 | |
a5c7d693 RS |
2436 | create_fixed_operand (&ops[0], targ0); |
2437 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
2438 | create_convert_operand_from (&ops[2], op1, mode, unsignedp); | |
2439 | create_fixed_operand (&ops[3], targ1); | |
2440 | if (maybe_expand_insn (icode, 4, ops)) | |
2441 | return 1; | |
2442 | delete_insns_since (last); | |
77c9c6c2 RK |
2443 | } |
2444 | ||
2445 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
2446 | ||
d858f359 | 2447 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 2448 | { |
86556d87 BE |
2449 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2450 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
2451 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2452 | { | |
947131ba | 2453 | if (optab_handler (binoptab, wider_mode) != CODE_FOR_nothing) |
77c9c6c2 | 2454 | { |
b3694847 SS |
2455 | rtx t0 = gen_reg_rtx (wider_mode); |
2456 | rtx t1 = gen_reg_rtx (wider_mode); | |
76791f3d JH |
2457 | rtx cop0 = convert_modes (wider_mode, mode, op0, unsignedp); |
2458 | rtx cop1 = convert_modes (wider_mode, mode, op1, unsignedp); | |
77c9c6c2 | 2459 | |
76791f3d | 2460 | if (expand_twoval_binop (binoptab, cop0, cop1, |
77c9c6c2 RK |
2461 | t0, t1, unsignedp)) |
2462 | { | |
2463 | convert_move (targ0, t0, unsignedp); | |
2464 | convert_move (targ1, t1, unsignedp); | |
2465 | return 1; | |
2466 | } | |
2467 | else | |
2468 | delete_insns_since (last); | |
2469 | } | |
2470 | } | |
2471 | } | |
2472 | ||
abd418d3 | 2473 | delete_insns_since (entry_last); |
77c9c6c2 RK |
2474 | return 0; |
2475 | } | |
b3f8d95d MM |
2476 | |
2477 | /* Expand the two-valued library call indicated by BINOPTAB, but | |
2478 | preserve only one of the values. If TARG0 is non-NULL, the first | |
2479 | value is placed into TARG0; otherwise the second value is placed | |
2480 | into TARG1. Exactly one of TARG0 and TARG1 must be non-NULL. The | |
2481 | value stored into TARG0 or TARG1 is equivalent to (CODE OP0 OP1). | |
2482 | This routine assumes that the value returned by the library call is | |
2483 | as if the return value was of an integral mode twice as wide as the | |
2484 | mode of OP0. Returns 1 if the call was successful. */ | |
2485 | ||
2486 | bool | |
5906d013 | 2487 | expand_twoval_binop_libfunc (optab binoptab, rtx op0, rtx op1, |
b3f8d95d MM |
2488 | rtx targ0, rtx targ1, enum rtx_code code) |
2489 | { | |
2490 | enum machine_mode mode; | |
2491 | enum machine_mode libval_mode; | |
2492 | rtx libval; | |
2493 | rtx insns; | |
8a33f100 | 2494 | rtx libfunc; |
5906d013 | 2495 | |
b3f8d95d | 2496 | /* Exactly one of TARG0 or TARG1 should be non-NULL. */ |
e3feb571 | 2497 | gcc_assert (!targ0 != !targ1); |
b3f8d95d MM |
2498 | |
2499 | mode = GET_MODE (op0); | |
8a33f100 JH |
2500 | libfunc = optab_libfunc (binoptab, mode); |
2501 | if (!libfunc) | |
b3f8d95d MM |
2502 | return false; |
2503 | ||
2504 | /* The value returned by the library function will have twice as | |
2505 | many bits as the nominal MODE. */ | |
5906d013 | 2506 | libval_mode = smallest_mode_for_size (2 * GET_MODE_BITSIZE (mode), |
b3f8d95d MM |
2507 | MODE_INT); |
2508 | start_sequence (); | |
8a33f100 | 2509 | libval = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
b3f8d95d | 2510 | libval_mode, 2, |
5906d013 | 2511 | op0, mode, |
b3f8d95d MM |
2512 | op1, mode); |
2513 | /* Get the part of VAL containing the value that we want. */ | |
2514 | libval = simplify_gen_subreg (mode, libval, libval_mode, | |
2515 | targ0 ? 0 : GET_MODE_SIZE (mode)); | |
2516 | insns = get_insns (); | |
2517 | end_sequence (); | |
2518 | /* Move the into the desired location. */ | |
5906d013 | 2519 | emit_libcall_block (insns, targ0 ? targ0 : targ1, libval, |
b3f8d95d | 2520 | gen_rtx_fmt_ee (code, mode, op0, op1)); |
5906d013 | 2521 | |
b3f8d95d MM |
2522 | return true; |
2523 | } | |
2524 | ||
77c9c6c2 | 2525 | \f |
ef89d648 ZW |
2526 | /* Wrapper around expand_unop which takes an rtx code to specify |
2527 | the operation to perform, not an optab pointer. All other | |
2528 | arguments are the same. */ | |
2529 | rtx | |
0c20a65f AJ |
2530 | expand_simple_unop (enum machine_mode mode, enum rtx_code code, rtx op0, |
2531 | rtx target, int unsignedp) | |
ef89d648 | 2532 | { |
19b5fafb | 2533 | optab unop = code_to_optab (code); |
e3feb571 | 2534 | gcc_assert (unop); |
ef89d648 ZW |
2535 | |
2536 | return expand_unop (mode, unop, op0, target, unsignedp); | |
2537 | } | |
2538 | ||
2928cd7a RH |
2539 | /* Try calculating |
2540 | (clz:narrow x) | |
2541 | as | |
3801c801 BS |
2542 | (clz:wide (zero_extend:wide x)) - ((width wide) - (width narrow)). |
2543 | ||
2544 | A similar operation can be used for clrsb. UNOPTAB says which operation | |
2545 | we are trying to expand. */ | |
2928cd7a | 2546 | static rtx |
3801c801 | 2547 | widen_leading (enum machine_mode mode, rtx op0, rtx target, optab unoptab) |
2928cd7a | 2548 | { |
d858f359 KG |
2549 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2550 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2551 | { |
2552 | enum machine_mode wider_mode; | |
86556d87 BE |
2553 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
2554 | wider_mode != VOIDmode; | |
2928cd7a RH |
2555 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
2556 | { | |
3801c801 | 2557 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2558 | { |
2559 | rtx xop0, temp, last; | |
2560 | ||
2561 | last = get_last_insn (); | |
2562 | ||
2563 | if (target == 0) | |
2564 | target = gen_reg_rtx (mode); | |
146aef0b JJ |
2565 | xop0 = widen_operand (op0, wider_mode, mode, |
2566 | unoptab != clrsb_optab, false); | |
2567 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, | |
2568 | unoptab != clrsb_optab); | |
2928cd7a | 2569 | if (temp != 0) |
2f1cd2eb RS |
2570 | temp = expand_binop |
2571 | (wider_mode, sub_optab, temp, | |
2572 | gen_int_mode (GET_MODE_PRECISION (wider_mode) | |
2573 | - GET_MODE_PRECISION (mode), | |
2574 | wider_mode), | |
2575 | target, true, OPTAB_DIRECT); | |
2928cd7a RH |
2576 | if (temp == 0) |
2577 | delete_insns_since (last); | |
2578 | ||
2579 | return temp; | |
2580 | } | |
2581 | } | |
2582 | } | |
2583 | return 0; | |
2584 | } | |
2585 | ||
9cce5b20 ZW |
2586 | /* Try calculating clz of a double-word quantity as two clz's of word-sized |
2587 | quantities, choosing which based on whether the high word is nonzero. */ | |
2588 | static rtx | |
2589 | expand_doubleword_clz (enum machine_mode mode, rtx op0, rtx target) | |
2590 | { | |
2591 | rtx xop0 = force_reg (mode, op0); | |
2592 | rtx subhi = gen_highpart (word_mode, xop0); | |
2593 | rtx sublo = gen_lowpart (word_mode, xop0); | |
2594 | rtx hi0_label = gen_label_rtx (); | |
2595 | rtx after_label = gen_label_rtx (); | |
2596 | rtx seq, temp, result; | |
2597 | ||
2598 | /* If we were not given a target, use a word_mode register, not a | |
2599 | 'mode' register. The result will fit, and nobody is expecting | |
2600 | anything bigger (the return type of __builtin_clz* is int). */ | |
2601 | if (!target) | |
2602 | target = gen_reg_rtx (word_mode); | |
2603 | ||
2604 | /* In any case, write to a word_mode scratch in both branches of the | |
2605 | conditional, so we can ensure there is a single move insn setting | |
2606 | 'target' to tag a REG_EQUAL note on. */ | |
2607 | result = gen_reg_rtx (word_mode); | |
2608 | ||
2609 | start_sequence (); | |
2610 | ||
2611 | /* If the high word is not equal to zero, | |
2612 | then clz of the full value is clz of the high word. */ | |
2613 | emit_cmp_and_jump_insns (subhi, CONST0_RTX (word_mode), EQ, 0, | |
2614 | word_mode, true, hi0_label); | |
2615 | ||
2616 | temp = expand_unop_direct (word_mode, clz_optab, subhi, result, true); | |
2617 | if (!temp) | |
2618 | goto fail; | |
2619 | ||
2620 | if (temp != result) | |
2621 | convert_move (result, temp, true); | |
2622 | ||
2623 | emit_jump_insn (gen_jump (after_label)); | |
2624 | emit_barrier (); | |
2625 | ||
2626 | /* Else clz of the full value is clz of the low word plus the number | |
2627 | of bits in the high word. */ | |
2628 | emit_label (hi0_label); | |
2629 | ||
2630 | temp = expand_unop_direct (word_mode, clz_optab, sublo, 0, true); | |
2631 | if (!temp) | |
2632 | goto fail; | |
2633 | temp = expand_binop (word_mode, add_optab, temp, | |
2f1cd2eb | 2634 | gen_int_mode (GET_MODE_BITSIZE (word_mode), word_mode), |
9cce5b20 ZW |
2635 | result, true, OPTAB_DIRECT); |
2636 | if (!temp) | |
2637 | goto fail; | |
2638 | if (temp != result) | |
2639 | convert_move (result, temp, true); | |
2640 | ||
2641 | emit_label (after_label); | |
2642 | convert_move (target, result, true); | |
2643 | ||
2644 | seq = get_insns (); | |
2645 | end_sequence (); | |
2646 | ||
2647 | add_equal_note (seq, target, CLZ, xop0, 0); | |
2648 | emit_insn (seq); | |
2649 | return target; | |
2650 | ||
2651 | fail: | |
2652 | end_sequence (); | |
2653 | return 0; | |
2654 | } | |
2655 | ||
2e6834d3 RH |
2656 | /* Try calculating |
2657 | (bswap:narrow x) | |
2658 | as | |
2659 | (lshiftrt:wide (bswap:wide x) ((width wide) - (width narrow))). */ | |
2660 | static rtx | |
2661 | widen_bswap (enum machine_mode mode, rtx op0, rtx target) | |
2662 | { | |
d858f359 | 2663 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2e6834d3 RH |
2664 | enum machine_mode wider_mode; |
2665 | rtx x, last; | |
2666 | ||
d858f359 | 2667 | if (!CLASS_HAS_WIDER_MODES_P (mclass)) |
2e6834d3 RH |
2668 | return NULL_RTX; |
2669 | ||
2670 | for (wider_mode = GET_MODE_WIDER_MODE (mode); | |
2671 | wider_mode != VOIDmode; | |
2672 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
947131ba | 2673 | if (optab_handler (bswap_optab, wider_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
2674 | goto found; |
2675 | return NULL_RTX; | |
2676 | ||
2677 | found: | |
2678 | last = get_last_insn (); | |
2679 | ||
2680 | x = widen_operand (op0, wider_mode, mode, true, true); | |
2681 | x = expand_unop (wider_mode, bswap_optab, x, NULL_RTX, true); | |
2682 | ||
0d44736e BS |
2683 | gcc_assert (GET_MODE_PRECISION (wider_mode) == GET_MODE_BITSIZE (wider_mode) |
2684 | && GET_MODE_PRECISION (mode) == GET_MODE_BITSIZE (mode)); | |
2e6834d3 RH |
2685 | if (x != 0) |
2686 | x = expand_shift (RSHIFT_EXPR, wider_mode, x, | |
eb6c3df1 RG |
2687 | GET_MODE_BITSIZE (wider_mode) |
2688 | - GET_MODE_BITSIZE (mode), | |
2e6834d3 RH |
2689 | NULL_RTX, true); |
2690 | ||
2691 | if (x != 0) | |
2692 | { | |
2693 | if (target == 0) | |
2694 | target = gen_reg_rtx (mode); | |
2695 | emit_move_insn (target, gen_lowpart (mode, x)); | |
2696 | } | |
2697 | else | |
2698 | delete_insns_since (last); | |
2699 | ||
2700 | return target; | |
2701 | } | |
2702 | ||
2703 | /* Try calculating bswap as two bswaps of two word-sized operands. */ | |
2704 | ||
2705 | static rtx | |
2706 | expand_doubleword_bswap (enum machine_mode mode, rtx op, rtx target) | |
2707 | { | |
2708 | rtx t0, t1; | |
2709 | ||
2710 | t1 = expand_unop (word_mode, bswap_optab, | |
2711 | operand_subword_force (op, 0, mode), NULL_RTX, true); | |
2712 | t0 = expand_unop (word_mode, bswap_optab, | |
2713 | operand_subword_force (op, 1, mode), NULL_RTX, true); | |
2714 | ||
02972eaf | 2715 | if (target == 0 || !valid_multiword_target_p (target)) |
2e6834d3 RH |
2716 | target = gen_reg_rtx (mode); |
2717 | if (REG_P (target)) | |
c41c1387 | 2718 | emit_clobber (target); |
2e6834d3 RH |
2719 | emit_move_insn (operand_subword (target, 0, 1, mode), t0); |
2720 | emit_move_insn (operand_subword (target, 1, 1, mode), t1); | |
2721 | ||
2722 | return target; | |
2723 | } | |
2724 | ||
2928cd7a RH |
2725 | /* Try calculating (parity x) as (and (popcount x) 1), where |
2726 | popcount can also be done in a wider mode. */ | |
2727 | static rtx | |
0c20a65f | 2728 | expand_parity (enum machine_mode mode, rtx op0, rtx target) |
2928cd7a | 2729 | { |
d858f359 KG |
2730 | enum mode_class mclass = GET_MODE_CLASS (mode); |
2731 | if (CLASS_HAS_WIDER_MODES_P (mclass)) | |
2928cd7a RH |
2732 | { |
2733 | enum machine_mode wider_mode; | |
2734 | for (wider_mode = mode; wider_mode != VOIDmode; | |
2735 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) | |
2736 | { | |
947131ba | 2737 | if (optab_handler (popcount_optab, wider_mode) != CODE_FOR_nothing) |
2928cd7a RH |
2738 | { |
2739 | rtx xop0, temp, last; | |
2740 | ||
2741 | last = get_last_insn (); | |
2742 | ||
2743 | if (target == 0) | |
2744 | target = gen_reg_rtx (mode); | |
2745 | xop0 = widen_operand (op0, wider_mode, mode, true, false); | |
2746 | temp = expand_unop (wider_mode, popcount_optab, xop0, NULL_RTX, | |
2747 | true); | |
2748 | if (temp != 0) | |
60c81c89 | 2749 | temp = expand_binop (wider_mode, and_optab, temp, const1_rtx, |
2928cd7a RH |
2750 | target, true, OPTAB_DIRECT); |
2751 | if (temp == 0) | |
2752 | delete_insns_since (last); | |
2753 | ||
2754 | return temp; | |
2755 | } | |
2756 | } | |
2757 | } | |
2758 | return 0; | |
2759 | } | |
2760 | ||
9cce5b20 | 2761 | /* Try calculating ctz(x) as K - clz(x & -x) , |
69660a70 | 2762 | where K is GET_MODE_PRECISION(mode) - 1. |
9cce5b20 ZW |
2763 | |
2764 | Both __builtin_ctz and __builtin_clz are undefined at zero, so we | |
2765 | don't have to worry about what the hardware does in that case. (If | |
2766 | the clz instruction produces the usual value at 0, which is K, the | |
2767 | result of this code sequence will be -1; expand_ffs, below, relies | |
2768 | on this. It might be nice to have it be K instead, for consistency | |
2769 | with the (very few) processors that provide a ctz with a defined | |
2770 | value, but that would take one more instruction, and it would be | |
2771 | less convenient for expand_ffs anyway. */ | |
2772 | ||
14670a74 | 2773 | static rtx |
9cce5b20 | 2774 | expand_ctz (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2775 | { |
9cce5b20 | 2776 | rtx seq, temp; |
b8698a0f | 2777 | |
947131ba | 2778 | if (optab_handler (clz_optab, mode) == CODE_FOR_nothing) |
9cce5b20 | 2779 | return 0; |
b8698a0f | 2780 | |
9cce5b20 | 2781 | start_sequence (); |
14670a74 | 2782 | |
9cce5b20 ZW |
2783 | temp = expand_unop_direct (mode, neg_optab, op0, NULL_RTX, true); |
2784 | if (temp) | |
2785 | temp = expand_binop (mode, and_optab, op0, temp, NULL_RTX, | |
2786 | true, OPTAB_DIRECT); | |
2787 | if (temp) | |
2788 | temp = expand_unop_direct (mode, clz_optab, temp, NULL_RTX, true); | |
2789 | if (temp) | |
2f1cd2eb RS |
2790 | temp = expand_binop (mode, sub_optab, |
2791 | gen_int_mode (GET_MODE_PRECISION (mode) - 1, mode), | |
9cce5b20 ZW |
2792 | temp, target, |
2793 | true, OPTAB_DIRECT); | |
2794 | if (temp == 0) | |
2795 | { | |
2796 | end_sequence (); | |
2797 | return 0; | |
14670a74 | 2798 | } |
9cce5b20 ZW |
2799 | |
2800 | seq = get_insns (); | |
2801 | end_sequence (); | |
2802 | ||
2803 | add_equal_note (seq, temp, CTZ, op0, 0); | |
2804 | emit_insn (seq); | |
2805 | return temp; | |
14670a74 SL |
2806 | } |
2807 | ||
9cce5b20 ZW |
2808 | |
2809 | /* Try calculating ffs(x) using ctz(x) if we have that instruction, or | |
2810 | else with the sequence used by expand_clz. | |
b8698a0f | 2811 | |
9cce5b20 ZW |
2812 | The ffs builtin promises to return zero for a zero value and ctz/clz |
2813 | may have an undefined value in that case. If they do not give us a | |
2814 | convenient value, we have to generate a test and branch. */ | |
14670a74 | 2815 | static rtx |
9cce5b20 | 2816 | expand_ffs (enum machine_mode mode, rtx op0, rtx target) |
14670a74 | 2817 | { |
a3324f26 ZW |
2818 | HOST_WIDE_INT val = 0; |
2819 | bool defined_at_zero = false; | |
9cce5b20 ZW |
2820 | rtx temp, seq; |
2821 | ||
947131ba | 2822 | if (optab_handler (ctz_optab, mode) != CODE_FOR_nothing) |
14670a74 | 2823 | { |
9cce5b20 | 2824 | start_sequence (); |
14670a74 | 2825 | |
9cce5b20 ZW |
2826 | temp = expand_unop_direct (mode, ctz_optab, op0, 0, true); |
2827 | if (!temp) | |
2828 | goto fail; | |
2829 | ||
2830 | defined_at_zero = (CTZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2); | |
14670a74 | 2831 | } |
947131ba | 2832 | else if (optab_handler (clz_optab, mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
2833 | { |
2834 | start_sequence (); | |
2835 | temp = expand_ctz (mode, op0, 0); | |
2836 | if (!temp) | |
2837 | goto fail; | |
2838 | ||
2839 | if (CLZ_DEFINED_VALUE_AT_ZERO (mode, val) == 2) | |
2840 | { | |
2841 | defined_at_zero = true; | |
69660a70 | 2842 | val = (GET_MODE_PRECISION (mode) - 1) - val; |
9cce5b20 ZW |
2843 | } |
2844 | } | |
2845 | else | |
2846 | return 0; | |
2847 | ||
2848 | if (defined_at_zero && val == -1) | |
2849 | /* No correction needed at zero. */; | |
b8698a0f | 2850 | else |
9cce5b20 ZW |
2851 | { |
2852 | /* We don't try to do anything clever with the situation found | |
2853 | on some processors (eg Alpha) where ctz(0:mode) == | |
2854 | bitsize(mode). If someone can think of a way to send N to -1 | |
2855 | and leave alone all values in the range 0..N-1 (where N is a | |
2856 | power of two), cheaper than this test-and-branch, please add it. | |
2857 | ||
2858 | The test-and-branch is done after the operation itself, in case | |
2859 | the operation sets condition codes that can be recycled for this. | |
2860 | (This is true on i386, for instance.) */ | |
2861 | ||
2862 | rtx nonzero_label = gen_label_rtx (); | |
2863 | emit_cmp_and_jump_insns (op0, CONST0_RTX (mode), NE, 0, | |
2864 | mode, true, nonzero_label); | |
2865 | ||
2866 | convert_move (temp, GEN_INT (-1), false); | |
2867 | emit_label (nonzero_label); | |
2868 | } | |
2869 | ||
2870 | /* temp now has a value in the range -1..bitsize-1. ffs is supposed | |
2871 | to produce a value in the range 0..bitsize. */ | |
2f1cd2eb | 2872 | temp = expand_binop (mode, add_optab, temp, gen_int_mode (1, mode), |
9cce5b20 ZW |
2873 | target, false, OPTAB_DIRECT); |
2874 | if (!temp) | |
2875 | goto fail; | |
2876 | ||
2877 | seq = get_insns (); | |
2878 | end_sequence (); | |
2879 | ||
2880 | add_equal_note (seq, temp, FFS, op0, 0); | |
2881 | emit_insn (seq); | |
2882 | return temp; | |
2883 | ||
2884 | fail: | |
2885 | end_sequence (); | |
14670a74 SL |
2886 | return 0; |
2887 | } | |
2888 | ||
c414ac1d | 2889 | /* Extract the OMODE lowpart from VAL, which has IMODE. Under certain |
6b132673 RH |
2890 | conditions, VAL may already be a SUBREG against which we cannot generate |
2891 | a further SUBREG. In this case, we expect forcing the value into a | |
2892 | register will work around the situation. */ | |
2893 | ||
2894 | static rtx | |
2895 | lowpart_subreg_maybe_copy (enum machine_mode omode, rtx val, | |
2896 | enum machine_mode imode) | |
2897 | { | |
2898 | rtx ret; | |
2899 | ret = lowpart_subreg (omode, val, imode); | |
2900 | if (ret == NULL) | |
2901 | { | |
2902 | val = force_reg (imode, val); | |
2903 | ret = lowpart_subreg (omode, val, imode); | |
2904 | gcc_assert (ret != NULL); | |
2905 | } | |
2906 | return ret; | |
2907 | } | |
2908 | ||
8c55a142 RH |
2909 | /* Expand a floating point absolute value or negation operation via a |
2910 | logical operation on the sign bit. */ | |
2911 | ||
2912 | static rtx | |
2913 | expand_absneg_bit (enum rtx_code code, enum machine_mode mode, | |
2914 | rtx op0, rtx target) | |
2915 | { | |
2916 | const struct real_format *fmt; | |
2917 | int bitpos, word, nwords, i; | |
2918 | enum machine_mode imode; | |
8c55a142 RH |
2919 | rtx temp, insns; |
2920 | ||
2921 | /* The format has to have a simple sign bit. */ | |
2922 | fmt = REAL_MODE_FORMAT (mode); | |
2923 | if (fmt == NULL) | |
2924 | return NULL_RTX; | |
2925 | ||
b87a0206 | 2926 | bitpos = fmt->signbit_rw; |
8c55a142 RH |
2927 | if (bitpos < 0) |
2928 | return NULL_RTX; | |
2929 | ||
2930 | /* Don't create negative zeros if the format doesn't support them. */ | |
2931 | if (code == NEG && !fmt->has_signed_zero) | |
2932 | return NULL_RTX; | |
2933 | ||
2934 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) | |
2935 | { | |
2936 | imode = int_mode_for_mode (mode); | |
2937 | if (imode == BLKmode) | |
2938 | return NULL_RTX; | |
2939 | word = 0; | |
2940 | nwords = 1; | |
2941 | } | |
2942 | else | |
2943 | { | |
2944 | imode = word_mode; | |
2945 | ||
2946 | if (FLOAT_WORDS_BIG_ENDIAN) | |
2947 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
2948 | else | |
2949 | word = bitpos / BITS_PER_WORD; | |
2950 | bitpos = bitpos % BITS_PER_WORD; | |
2951 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
2952 | } | |
2953 | ||
807e902e | 2954 | wide_int mask = wi::set_bit_in_zero (bitpos, GET_MODE_PRECISION (imode)); |
8c55a142 | 2955 | if (code == ABS) |
27bcd47c | 2956 | mask = ~mask; |
8c55a142 | 2957 | |
02972eaf RS |
2958 | if (target == 0 |
2959 | || target == op0 | |
2960 | || (nwords > 1 && !valid_multiword_target_p (target))) | |
8c55a142 RH |
2961 | target = gen_reg_rtx (mode); |
2962 | ||
2963 | if (nwords > 1) | |
2964 | { | |
2965 | start_sequence (); | |
2966 | ||
2967 | for (i = 0; i < nwords; ++i) | |
2968 | { | |
2969 | rtx targ_piece = operand_subword (target, i, 1, mode); | |
2970 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 2971 | |
8c55a142 RH |
2972 | if (i == word) |
2973 | { | |
2974 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2975 | op0_piece, | |
807e902e | 2976 | immed_wide_int_const (mask, imode), |
8c55a142 RH |
2977 | targ_piece, 1, OPTAB_LIB_WIDEN); |
2978 | if (temp != targ_piece) | |
2979 | emit_move_insn (targ_piece, temp); | |
2980 | } | |
2981 | else | |
2982 | emit_move_insn (targ_piece, op0_piece); | |
2983 | } | |
2984 | ||
2985 | insns = get_insns (); | |
2986 | end_sequence (); | |
2987 | ||
d70dcf29 | 2988 | emit_insn (insns); |
8c55a142 RH |
2989 | } |
2990 | else | |
2991 | { | |
2992 | temp = expand_binop (imode, code == ABS ? and_optab : xor_optab, | |
2993 | gen_lowpart (imode, op0), | |
807e902e | 2994 | immed_wide_int_const (mask, imode), |
8c55a142 RH |
2995 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); |
2996 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
2997 | ||
7543f918 JR |
2998 | set_dst_reg_note (get_last_insn (), REG_EQUAL, |
2999 | gen_rtx_fmt_e (code, mode, copy_rtx (op0)), | |
3000 | target); | |
8c55a142 RH |
3001 | } |
3002 | ||
3003 | return target; | |
3004 | } | |
3005 | ||
9cce5b20 ZW |
3006 | /* As expand_unop, but will fail rather than attempt the operation in a |
3007 | different mode or with a libcall. */ | |
3008 | static rtx | |
3009 | expand_unop_direct (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
0c20a65f | 3010 | int unsignedp) |
77c9c6c2 | 3011 | { |
947131ba | 3012 | if (optab_handler (unoptab, mode) != CODE_FOR_nothing) |
77c9c6c2 | 3013 | { |
a5c7d693 RS |
3014 | struct expand_operand ops[2]; |
3015 | enum insn_code icode = optab_handler (unoptab, mode); | |
9cce5b20 | 3016 | rtx last = get_last_insn (); |
a5c7d693 | 3017 | rtx pat; |
77c9c6c2 | 3018 | |
a5c7d693 RS |
3019 | create_output_operand (&ops[0], target, mode); |
3020 | create_convert_operand_from (&ops[1], op0, mode, unsignedp); | |
3021 | pat = maybe_gen_insn (icode, 2, ops); | |
77c9c6c2 RK |
3022 | if (pat) |
3023 | { | |
2f937369 | 3024 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX |
19b5fafb | 3025 | && ! add_equal_note (pat, ops[0].value, optab_to_code (unoptab), |
a5c7d693 | 3026 | ops[1].value, NULL_RTX)) |
77c9c6c2 RK |
3027 | { |
3028 | delete_insns_since (last); | |
b1ec3c92 | 3029 | return expand_unop (mode, unoptab, op0, NULL_RTX, unsignedp); |
77c9c6c2 RK |
3030 | } |
3031 | ||
3032 | emit_insn (pat); | |
0c20a65f | 3033 | |
a5c7d693 | 3034 | return ops[0].value; |
77c9c6c2 | 3035 | } |
77c9c6c2 | 3036 | } |
9cce5b20 ZW |
3037 | return 0; |
3038 | } | |
3039 | ||
3040 | /* Generate code to perform an operation specified by UNOPTAB | |
3041 | on operand OP0, with result having machine-mode MODE. | |
3042 | ||
3043 | UNSIGNEDP is for the case where we have to widen the operands | |
3044 | to perform the operation. It says to use zero-extension. | |
3045 | ||
3046 | If TARGET is nonzero, the value | |
3047 | is generated there, if it is convenient to do so. | |
3048 | In all cases an rtx is returned for the locus of the value; | |
3049 | this may or may not be TARGET. */ | |
3050 | ||
3051 | rtx | |
3052 | expand_unop (enum machine_mode mode, optab unoptab, rtx op0, rtx target, | |
3053 | int unsignedp) | |
3054 | { | |
d858f359 | 3055 | enum mode_class mclass = GET_MODE_CLASS (mode); |
9cce5b20 ZW |
3056 | enum machine_mode wider_mode; |
3057 | rtx temp; | |
8a33f100 | 3058 | rtx libfunc; |
9cce5b20 ZW |
3059 | |
3060 | temp = expand_unop_direct (mode, unoptab, op0, target, unsignedp); | |
3061 | if (temp) | |
3062 | return temp; | |
77c9c6c2 | 3063 | |
9a856ec7 RK |
3064 | /* It can't be done in this mode. Can we open-code it in a wider mode? */ |
3065 | ||
9cce5b20 | 3066 | /* Widening (or narrowing) clz needs special treatment. */ |
2928cd7a RH |
3067 | if (unoptab == clz_optab) |
3068 | { | |
3801c801 | 3069 | temp = widen_leading (mode, op0, target, unoptab); |
2928cd7a RH |
3070 | if (temp) |
3071 | return temp; | |
9cce5b20 ZW |
3072 | |
3073 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 3074 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
9cce5b20 ZW |
3075 | { |
3076 | temp = expand_doubleword_clz (mode, op0, target); | |
3077 | if (temp) | |
3078 | return temp; | |
3079 | } | |
3080 | ||
3801c801 BS |
3081 | goto try_libcall; |
3082 | } | |
3083 | ||
3084 | if (unoptab == clrsb_optab) | |
3085 | { | |
3086 | temp = widen_leading (mode, op0, target, unoptab); | |
3087 | if (temp) | |
3088 | return temp; | |
3089 | goto try_libcall; | |
2928cd7a RH |
3090 | } |
3091 | ||
2e6834d3 | 3092 | /* Widening (or narrowing) bswap needs special treatment. */ |
167fa32c | 3093 | if (unoptab == bswap_optab) |
2e6834d3 | 3094 | { |
ac868f29 EB |
3095 | /* HImode is special because in this mode BSWAP is equivalent to ROTATE |
3096 | or ROTATERT. First try these directly; if this fails, then try the | |
3097 | obvious pair of shifts with allowed widening, as this will probably | |
3098 | be always more efficient than the other fallback methods. */ | |
3099 | if (mode == HImode) | |
3100 | { | |
3101 | rtx last, temp1, temp2; | |
3102 | ||
3103 | if (optab_handler (rotl_optab, mode) != CODE_FOR_nothing) | |
3104 | { | |
3105 | temp = expand_binop (mode, rotl_optab, op0, GEN_INT (8), target, | |
3106 | unsignedp, OPTAB_DIRECT); | |
3107 | if (temp) | |
3108 | return temp; | |
3109 | } | |
3110 | ||
3111 | if (optab_handler (rotr_optab, mode) != CODE_FOR_nothing) | |
3112 | { | |
3113 | temp = expand_binop (mode, rotr_optab, op0, GEN_INT (8), target, | |
3114 | unsignedp, OPTAB_DIRECT); | |
3115 | if (temp) | |
3116 | return temp; | |
3117 | } | |
3118 | ||
3119 | last = get_last_insn (); | |
3120 | ||
3121 | temp1 = expand_binop (mode, ashl_optab, op0, GEN_INT (8), NULL_RTX, | |
3122 | unsignedp, OPTAB_WIDEN); | |
3123 | temp2 = expand_binop (mode, lshr_optab, op0, GEN_INT (8), NULL_RTX, | |
3124 | unsignedp, OPTAB_WIDEN); | |
3125 | if (temp1 && temp2) | |
3126 | { | |
3127 | temp = expand_binop (mode, ior_optab, temp1, temp2, target, | |
3128 | unsignedp, OPTAB_WIDEN); | |
3129 | if (temp) | |
3130 | return temp; | |
3131 | } | |
3132 | ||
3133 | delete_insns_since (last); | |
3134 | } | |
3135 | ||
2e6834d3 RH |
3136 | temp = widen_bswap (mode, op0, target); |
3137 | if (temp) | |
3138 | return temp; | |
3139 | ||
3140 | if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_WORD | |
947131ba | 3141 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
2e6834d3 RH |
3142 | { |
3143 | temp = expand_doubleword_bswap (mode, op0, target); | |
3144 | if (temp) | |
3145 | return temp; | |
3146 | } | |
3147 | ||
3148 | goto try_libcall; | |
3149 | } | |
167fa32c | 3150 | |
d858f359 | 3151 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
86556d87 BE |
3152 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3153 | wider_mode != VOIDmode; | |
9a856ec7 RK |
3154 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3155 | { | |
947131ba | 3156 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing) |
9a856ec7 RK |
3157 | { |
3158 | rtx xop0 = op0; | |
9cce5b20 | 3159 | rtx last = get_last_insn (); |
9a856ec7 RK |
3160 | |
3161 | /* For certain operations, we need not actually extend | |
3162 | the narrow operand, as long as we will truncate the | |
835532b8 RK |
3163 | results to the same narrowness. */ |
3164 | ||
0661a3de | 3165 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 RK |
3166 | (unoptab == neg_optab |
3167 | || unoptab == one_cmpl_optab) | |
d858f359 | 3168 | && mclass == MODE_INT); |
0c20a65f | 3169 | |
b1ec3c92 CH |
3170 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3171 | unsignedp); | |
9a856ec7 RK |
3172 | |
3173 | if (temp) | |
3174 | { | |
d858f359 | 3175 | if (mclass != MODE_INT |
d0edd768 | 3176 | || !TRULY_NOOP_TRUNCATION_MODES_P (mode, wider_mode)) |
9a856ec7 RK |
3177 | { |
3178 | if (target == 0) | |
3179 | target = gen_reg_rtx (mode); | |
3180 | convert_move (target, temp, 0); | |
3181 | return target; | |
3182 | } | |
3183 | else | |
3184 | return gen_lowpart (mode, temp); | |
3185 | } | |
3186 | else | |
3187 | delete_insns_since (last); | |
3188 | } | |
3189 | } | |
3190 | ||
77c9c6c2 RK |
3191 | /* These can be done a word at a time. */ |
3192 | if (unoptab == one_cmpl_optab | |
d858f359 | 3193 | && mclass == MODE_INT |
77c9c6c2 | 3194 | && GET_MODE_SIZE (mode) > UNITS_PER_WORD |
947131ba | 3195 | && optab_handler (unoptab, word_mode) != CODE_FOR_nothing) |
77c9c6c2 | 3196 | { |
bb93b973 | 3197 | int i; |
77c9c6c2 RK |
3198 | rtx insns; |
3199 | ||
02972eaf | 3200 | if (target == 0 || target == op0 || !valid_multiword_target_p (target)) |
77c9c6c2 RK |
3201 | target = gen_reg_rtx (mode); |
3202 | ||
3203 | start_sequence (); | |
3204 | ||
3205 | /* Do the actual arithmetic. */ | |
3206 | for (i = 0; i < GET_MODE_BITSIZE (mode) / BITS_PER_WORD; i++) | |
3207 | { | |
3208 | rtx target_piece = operand_subword (target, i, 1, mode); | |
34e56753 | 3209 | rtx x = expand_unop (word_mode, unoptab, |
77c9c6c2 RK |
3210 | operand_subword_force (op0, i, mode), |
3211 | target_piece, unsignedp); | |
bb93b973 | 3212 | |
77c9c6c2 RK |
3213 | if (target_piece != x) |
3214 | emit_move_insn (target_piece, x); | |
3215 | } | |
3216 | ||
3217 | insns = get_insns (); | |
3218 | end_sequence (); | |
3219 | ||
d70dcf29 | 3220 | emit_insn (insns); |
77c9c6c2 RK |
3221 | return target; |
3222 | } | |
3223 | ||
19b5fafb | 3224 | if (optab_to_code (unoptab) == NEG) |
4977bab6 | 3225 | { |
8c55a142 | 3226 | /* Try negating floating point values by flipping the sign bit. */ |
74b14698 | 3227 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3228 | { |
8c55a142 RH |
3229 | temp = expand_absneg_bit (NEG, mode, op0, target); |
3230 | if (temp) | |
3231 | return temp; | |
3232 | } | |
9ee0a442 | 3233 | |
8c55a142 RH |
3234 | /* If there is no negation pattern, and we have no negative zero, |
3235 | try subtracting from zero. */ | |
3236 | if (!HONOR_SIGNED_ZEROS (mode)) | |
3237 | { | |
3238 | temp = expand_binop (mode, (unoptab == negv_optab | |
3239 | ? subv_optab : sub_optab), | |
3240 | CONST0_RTX (mode), op0, target, | |
3241 | unsignedp, OPTAB_DIRECT); | |
3242 | if (temp) | |
3243 | return temp; | |
3244 | } | |
4977bab6 ZW |
3245 | } |
3246 | ||
2928cd7a RH |
3247 | /* Try calculating parity (x) as popcount (x) % 2. */ |
3248 | if (unoptab == parity_optab) | |
3249 | { | |
3250 | temp = expand_parity (mode, op0, target); | |
3251 | if (temp) | |
3252 | return temp; | |
3253 | } | |
3254 | ||
14670a74 SL |
3255 | /* Try implementing ffs (x) in terms of clz (x). */ |
3256 | if (unoptab == ffs_optab) | |
3257 | { | |
3258 | temp = expand_ffs (mode, op0, target); | |
3259 | if (temp) | |
3260 | return temp; | |
3261 | } | |
3262 | ||
3263 | /* Try implementing ctz (x) in terms of clz (x). */ | |
3264 | if (unoptab == ctz_optab) | |
3265 | { | |
3266 | temp = expand_ctz (mode, op0, target); | |
3267 | if (temp) | |
3268 | return temp; | |
3269 | } | |
3270 | ||
2928cd7a | 3271 | try_libcall: |
139e5e08 | 3272 | /* Now try a library call in this mode. */ |
8a33f100 JH |
3273 | libfunc = optab_libfunc (unoptab, mode); |
3274 | if (libfunc) | |
77c9c6c2 RK |
3275 | { |
3276 | rtx insns; | |
9a7f678c | 3277 | rtx value; |
1230d7f8 | 3278 | rtx eq_value; |
2928cd7a RH |
3279 | enum machine_mode outmode = mode; |
3280 | ||
3281 | /* All of these functions return small values. Thus we choose to | |
3282 | have them return something that isn't a double-word. */ | |
3283 | if (unoptab == ffs_optab || unoptab == clz_optab || unoptab == ctz_optab | |
3801c801 BS |
3284 | || unoptab == clrsb_optab || unoptab == popcount_optab |
3285 | || unoptab == parity_optab) | |
cd2ac05b | 3286 | outmode |
390b17c2 RE |
3287 | = GET_MODE (hard_libcall_value (TYPE_MODE (integer_type_node), |
3288 | optab_libfunc (unoptab, mode))); | |
77c9c6c2 RK |
3289 | |
3290 | start_sequence (); | |
3291 | ||
3292 | /* Pass 1 for NO_QUEUE so we don't lose any increments | |
3293 | if the libcall is cse'd or moved. */ | |
8a33f100 | 3294 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, outmode, |
2928cd7a | 3295 | 1, op0, mode); |
77c9c6c2 RK |
3296 | insns = get_insns (); |
3297 | end_sequence (); | |
3298 | ||
2928cd7a | 3299 | target = gen_reg_rtx (outmode); |
19b5fafb | 3300 | eq_value = gen_rtx_fmt_e (optab_to_code (unoptab), mode, op0); |
1230d7f8 RS |
3301 | if (GET_MODE_SIZE (outmode) < GET_MODE_SIZE (mode)) |
3302 | eq_value = simplify_gen_unary (TRUNCATE, outmode, eq_value, mode); | |
3303 | else if (GET_MODE_SIZE (outmode) > GET_MODE_SIZE (mode)) | |
3304 | eq_value = simplify_gen_unary (ZERO_EXTEND, outmode, eq_value, mode); | |
b55f62cc RG |
3305 | emit_libcall_block_1 (insns, target, value, eq_value, |
3306 | trapv_unoptab_p (unoptab)); | |
77c9c6c2 RK |
3307 | |
3308 | return target; | |
3309 | } | |
3310 | ||
3311 | /* It can't be done in this mode. Can we do it in a wider mode? */ | |
3312 | ||
d858f359 | 3313 | if (CLASS_HAS_WIDER_MODES_P (mclass)) |
77c9c6c2 | 3314 | { |
86556d87 BE |
3315 | for (wider_mode = GET_MODE_WIDER_MODE (mode); |
3316 | wider_mode != VOIDmode; | |
77c9c6c2 RK |
3317 | wider_mode = GET_MODE_WIDER_MODE (wider_mode)) |
3318 | { | |
947131ba | 3319 | if (optab_handler (unoptab, wider_mode) != CODE_FOR_nothing |
8a33f100 | 3320 | || optab_libfunc (unoptab, wider_mode)) |
77c9c6c2 | 3321 | { |
34e56753 | 3322 | rtx xop0 = op0; |
9cce5b20 | 3323 | rtx last = get_last_insn (); |
34e56753 RS |
3324 | |
3325 | /* For certain operations, we need not actually extend | |
3326 | the narrow operand, as long as we will truncate the | |
3327 | results to the same narrowness. */ | |
0661a3de | 3328 | xop0 = widen_operand (xop0, wider_mode, mode, unsignedp, |
835532b8 | 3329 | (unoptab == neg_optab |
ac868f29 EB |
3330 | || unoptab == one_cmpl_optab |
3331 | || unoptab == bswap_optab) | |
d858f359 | 3332 | && mclass == MODE_INT); |
0c20a65f | 3333 | |
b1ec3c92 CH |
3334 | temp = expand_unop (wider_mode, unoptab, xop0, NULL_RTX, |
3335 | unsignedp); | |
34e56753 | 3336 | |
c117dddc | 3337 | /* If we are generating clz using wider mode, adjust the |
146aef0b JJ |
3338 | result. Similarly for clrsb. */ |
3339 | if ((unoptab == clz_optab || unoptab == clrsb_optab) | |
3340 | && temp != 0) | |
2f1cd2eb RS |
3341 | temp = expand_binop |
3342 | (wider_mode, sub_optab, temp, | |
3343 | gen_int_mode (GET_MODE_PRECISION (wider_mode) | |
3344 | - GET_MODE_PRECISION (mode), | |
3345 | wider_mode), | |
3346 | target, true, OPTAB_DIRECT); | |
c117dddc | 3347 | |
ac868f29 EB |
3348 | /* Likewise for bswap. */ |
3349 | if (unoptab == bswap_optab && temp != 0) | |
3350 | { | |
3351 | gcc_assert (GET_MODE_PRECISION (wider_mode) | |
3352 | == GET_MODE_BITSIZE (wider_mode) | |
3353 | && GET_MODE_PRECISION (mode) | |
3354 | == GET_MODE_BITSIZE (mode)); | |
3355 | ||
3356 | temp = expand_shift (RSHIFT_EXPR, wider_mode, temp, | |
3357 | GET_MODE_BITSIZE (wider_mode) | |
3358 | - GET_MODE_BITSIZE (mode), | |
3359 | NULL_RTX, true); | |
3360 | } | |
3361 | ||
34e56753 | 3362 | if (temp) |
77c9c6c2 | 3363 | { |
d858f359 | 3364 | if (mclass != MODE_INT) |
34e56753 RS |
3365 | { |
3366 | if (target == 0) | |
3367 | target = gen_reg_rtx (mode); | |
3368 | convert_move (target, temp, 0); | |
3369 | return target; | |
3370 | } | |
3371 | else | |
3372 | return gen_lowpart (mode, temp); | |
77c9c6c2 RK |
3373 | } |
3374 | else | |
34e56753 | 3375 | delete_insns_since (last); |
77c9c6c2 RK |
3376 | } |
3377 | } | |
3378 | } | |
3379 | ||
8c55a142 RH |
3380 | /* One final attempt at implementing negation via subtraction, |
3381 | this time allowing widening of the operand. */ | |
19b5fafb | 3382 | if (optab_to_code (unoptab) == NEG && !HONOR_SIGNED_ZEROS (mode)) |
0c20a65f | 3383 | { |
b82b6eea | 3384 | rtx temp; |
91ce572a CC |
3385 | temp = expand_binop (mode, |
3386 | unoptab == negv_optab ? subv_optab : sub_optab, | |
3387 | CONST0_RTX (mode), op0, | |
3388 | target, unsignedp, OPTAB_LIB_WIDEN); | |
b82b6eea | 3389 | if (temp) |
8c55a142 | 3390 | return temp; |
b82b6eea | 3391 | } |
0c20a65f | 3392 | |
77c9c6c2 RK |
3393 | return 0; |
3394 | } | |
3395 | \f | |
decdfa82 RS |
3396 | /* Emit code to compute the absolute value of OP0, with result to |
3397 | TARGET if convenient. (TARGET may be 0.) The return value says | |
3398 | where the result actually is to be found. | |
3399 | ||
3400 | MODE is the mode of the operand; the mode of the result is | |
3401 | different but can be deduced from MODE. | |
3402 | ||
91813b28 | 3403 | */ |
7fd01431 RK |
3404 | |
3405 | rtx | |
0c20a65f AJ |
3406 | expand_abs_nojump (enum machine_mode mode, rtx op0, rtx target, |
3407 | int result_unsignedp) | |
7fd01431 | 3408 | { |
2ef0a555 | 3409 | rtx temp; |
7fd01431 | 3410 | |
dad16761 RB |
3411 | if (GET_MODE_CLASS (mode) != MODE_INT |
3412 | || ! flag_trapv) | |
91ce572a CC |
3413 | result_unsignedp = 1; |
3414 | ||
7fd01431 | 3415 | /* First try to do it with a special abs instruction. */ |
91ce572a CC |
3416 | temp = expand_unop (mode, result_unsignedp ? abs_optab : absv_optab, |
3417 | op0, target, 0); | |
7fd01431 RK |
3418 | if (temp != 0) |
3419 | return temp; | |
3420 | ||
4977bab6 | 3421 | /* For floating point modes, try clearing the sign bit. */ |
3d8bf70f | 3422 | if (SCALAR_FLOAT_MODE_P (mode)) |
4977bab6 | 3423 | { |
8c55a142 RH |
3424 | temp = expand_absneg_bit (ABS, mode, op0, target); |
3425 | if (temp) | |
3426 | return temp; | |
4977bab6 ZW |
3427 | } |
3428 | ||
14a774a9 | 3429 | /* If we have a MAX insn, we can do this as MAX (x, -x). */ |
947131ba | 3430 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing |
8c55a142 | 3431 | && !HONOR_SIGNED_ZEROS (mode)) |
14a774a9 RK |
3432 | { |
3433 | rtx last = get_last_insn (); | |
3434 | ||
dad16761 RB |
3435 | temp = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3436 | op0, NULL_RTX, 0); | |
14a774a9 RK |
3437 | if (temp != 0) |
3438 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3439 | OPTAB_WIDEN); | |
3440 | ||
3441 | if (temp != 0) | |
3442 | return temp; | |
3443 | ||
3444 | delete_insns_since (last); | |
3445 | } | |
3446 | ||
7fd01431 RK |
3447 | /* If this machine has expensive jumps, we can do integer absolute |
3448 | value of X as (((signed) x >> (W-1)) ^ x) - ((signed) x >> (W-1)), | |
e1078cfc | 3449 | where W is the width of MODE. */ |
7fd01431 | 3450 | |
3a4fd356 JH |
3451 | if (GET_MODE_CLASS (mode) == MODE_INT |
3452 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3453 | false) >= 2) | |
7fd01431 RK |
3454 | { |
3455 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
69660a70 | 3456 | GET_MODE_PRECISION (mode) - 1, |
7fd01431 RK |
3457 | NULL_RTX, 0); |
3458 | ||
3459 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3460 | OPTAB_LIB_WIDEN); | |
3461 | if (temp != 0) | |
91ce572a CC |
3462 | temp = expand_binop (mode, result_unsignedp ? sub_optab : subv_optab, |
3463 | temp, extended, target, 0, OPTAB_LIB_WIDEN); | |
7fd01431 RK |
3464 | |
3465 | if (temp != 0) | |
3466 | return temp; | |
3467 | } | |
3468 | ||
2ef0a555 RH |
3469 | return NULL_RTX; |
3470 | } | |
3471 | ||
3472 | rtx | |
0c20a65f AJ |
3473 | expand_abs (enum machine_mode mode, rtx op0, rtx target, |
3474 | int result_unsignedp, int safe) | |
2ef0a555 RH |
3475 | { |
3476 | rtx temp, op1; | |
3477 | ||
dad16761 RB |
3478 | if (GET_MODE_CLASS (mode) != MODE_INT |
3479 | || ! flag_trapv) | |
77173bbe KH |
3480 | result_unsignedp = 1; |
3481 | ||
2ef0a555 RH |
3482 | temp = expand_abs_nojump (mode, op0, target, result_unsignedp); |
3483 | if (temp != 0) | |
3484 | return temp; | |
3485 | ||
7fd01431 | 3486 | /* If that does not win, use conditional jump and negate. */ |
5c0bf747 RK |
3487 | |
3488 | /* It is safe to use the target if it is the same | |
3489 | as the source if this is also a pseudo register */ | |
f8cfc6aa | 3490 | if (op0 == target && REG_P (op0) |
5c0bf747 RK |
3491 | && REGNO (op0) >= FIRST_PSEUDO_REGISTER) |
3492 | safe = 1; | |
3493 | ||
7fd01431 RK |
3494 | op1 = gen_label_rtx (); |
3495 | if (target == 0 || ! safe | |
3496 | || GET_MODE (target) != mode | |
3c0cb5de | 3497 | || (MEM_P (target) && MEM_VOLATILE_P (target)) |
f8cfc6aa | 3498 | || (REG_P (target) |
7fd01431 RK |
3499 | && REGNO (target) < FIRST_PSEUDO_REGISTER)) |
3500 | target = gen_reg_rtx (mode); | |
3501 | ||
3502 | emit_move_insn (target, op0); | |
3503 | NO_DEFER_POP; | |
3504 | ||
3bf78d3b | 3505 | do_compare_rtx_and_jump (target, CONST0_RTX (mode), GE, 0, mode, |
40e90eac | 3506 | NULL_RTX, NULL_RTX, op1, -1); |
7fd01431 | 3507 | |
91ce572a CC |
3508 | op0 = expand_unop (mode, result_unsignedp ? neg_optab : negv_optab, |
3509 | target, target, 0); | |
7fd01431 RK |
3510 | if (op0 != target) |
3511 | emit_move_insn (target, op0); | |
3512 | emit_label (op1); | |
3513 | OK_DEFER_POP; | |
3514 | return target; | |
3515 | } | |
046625fa | 3516 | |
65026047 ER |
3517 | /* Emit code to compute the one's complement absolute value of OP0 |
3518 | (if (OP0 < 0) OP0 = ~OP0), with result to TARGET if convenient. | |
3519 | (TARGET may be NULL_RTX.) The return value says where the result | |
3520 | actually is to be found. | |
3521 | ||
3522 | MODE is the mode of the operand; the mode of the result is | |
3523 | different but can be deduced from MODE. */ | |
3524 | ||
3525 | rtx | |
3526 | expand_one_cmpl_abs_nojump (enum machine_mode mode, rtx op0, rtx target) | |
3527 | { | |
3528 | rtx temp; | |
3529 | ||
3530 | /* Not applicable for floating point modes. */ | |
3531 | if (FLOAT_MODE_P (mode)) | |
3532 | return NULL_RTX; | |
3533 | ||
3534 | /* If we have a MAX insn, we can do this as MAX (x, ~x). */ | |
947131ba | 3535 | if (optab_handler (smax_optab, mode) != CODE_FOR_nothing) |
65026047 ER |
3536 | { |
3537 | rtx last = get_last_insn (); | |
3538 | ||
3539 | temp = expand_unop (mode, one_cmpl_optab, op0, NULL_RTX, 0); | |
3540 | if (temp != 0) | |
3541 | temp = expand_binop (mode, smax_optab, op0, temp, target, 0, | |
3542 | OPTAB_WIDEN); | |
3543 | ||
3544 | if (temp != 0) | |
3545 | return temp; | |
3546 | ||
3547 | delete_insns_since (last); | |
3548 | } | |
3549 | ||
3550 | /* If this machine has expensive jumps, we can do one's complement | |
3551 | absolute value of X as (((signed) x >> (W-1)) ^ x). */ | |
3552 | ||
3553 | if (GET_MODE_CLASS (mode) == MODE_INT | |
3554 | && BRANCH_COST (optimize_insn_for_speed_p (), | |
3555 | false) >= 2) | |
3556 | { | |
3557 | rtx extended = expand_shift (RSHIFT_EXPR, mode, op0, | |
69660a70 | 3558 | GET_MODE_PRECISION (mode) - 1, |
65026047 ER |
3559 | NULL_RTX, 0); |
3560 | ||
3561 | temp = expand_binop (mode, xor_optab, extended, op0, target, 0, | |
3562 | OPTAB_LIB_WIDEN); | |
3563 | ||
3564 | if (temp != 0) | |
3565 | return temp; | |
3566 | } | |
3567 | ||
3568 | return NULL_RTX; | |
3569 | } | |
3570 | ||
ae394659 RH |
3571 | /* A subroutine of expand_copysign, perform the copysign operation using the |
3572 | abs and neg primitives advertised to exist on the target. The assumption | |
3573 | is that we have a split register file, and leaving op0 in fp registers, | |
3574 | and not playing with subregs so much, will help the register allocator. */ | |
046625fa | 3575 | |
9abd1955 | 3576 | static rtx |
ae394659 RH |
3577 | expand_copysign_absneg (enum machine_mode mode, rtx op0, rtx op1, rtx target, |
3578 | int bitpos, bool op0_is_abs) | |
046625fa | 3579 | { |
046625fa | 3580 | enum machine_mode imode; |
a5c7d693 | 3581 | enum insn_code icode; |
d0c9d431 | 3582 | rtx sign, label; |
046625fa | 3583 | |
ae394659 RH |
3584 | if (target == op1) |
3585 | target = NULL_RTX; | |
046625fa | 3586 | |
d0c9d431 UB |
3587 | /* Check if the back end provides an insn that handles signbit for the |
3588 | argument's mode. */ | |
a5c7d693 | 3589 | icode = optab_handler (signbit_optab, mode); |
d0c9d431 | 3590 | if (icode != CODE_FOR_nothing) |
ae394659 | 3591 | { |
a5c7d693 | 3592 | imode = insn_data[(int) icode].operand[0].mode; |
d0c9d431 UB |
3593 | sign = gen_reg_rtx (imode); |
3594 | emit_unop_insn (icode, sign, op1, UNKNOWN); | |
ae394659 RH |
3595 | } |
3596 | else | |
3597 | { | |
d0c9d431 UB |
3598 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
3599 | { | |
3600 | imode = int_mode_for_mode (mode); | |
3601 | if (imode == BLKmode) | |
3602 | return NULL_RTX; | |
3603 | op1 = gen_lowpart (imode, op1); | |
3604 | } | |
ae394659 | 3605 | else |
d0c9d431 UB |
3606 | { |
3607 | int word; | |
046625fa | 3608 | |
d0c9d431 UB |
3609 | imode = word_mode; |
3610 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3611 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3612 | else | |
3613 | word = bitpos / BITS_PER_WORD; | |
3614 | bitpos = bitpos % BITS_PER_WORD; | |
3615 | op1 = operand_subword_force (op1, word, mode); | |
3616 | } | |
3617 | ||
807e902e | 3618 | wide_int mask = wi::set_bit_in_zero (bitpos, GET_MODE_PRECISION (imode)); |
d0c9d431 | 3619 | sign = expand_binop (imode, and_optab, op1, |
807e902e | 3620 | immed_wide_int_const (mask, imode), |
d0c9d431 | 3621 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
ae394659 | 3622 | } |
046625fa | 3623 | |
d0c9d431 | 3624 | if (!op0_is_abs) |
8c55a142 | 3625 | { |
d0c9d431 UB |
3626 | op0 = expand_unop (mode, abs_optab, op0, target, 0); |
3627 | if (op0 == NULL) | |
3628 | return NULL_RTX; | |
3629 | target = op0; | |
8c55a142 | 3630 | } |
ae394659 RH |
3631 | else |
3632 | { | |
d0c9d431 UB |
3633 | if (target == NULL_RTX) |
3634 | target = copy_to_reg (op0); | |
3635 | else | |
3636 | emit_move_insn (target, op0); | |
ae394659 RH |
3637 | } |
3638 | ||
ae394659 | 3639 | label = gen_label_rtx (); |
d0c9d431 | 3640 | emit_cmp_and_jump_insns (sign, const0_rtx, EQ, NULL_RTX, imode, 1, label); |
ae394659 | 3641 | |
48175537 | 3642 | if (CONST_DOUBLE_AS_FLOAT_P (op0)) |
ae394659 RH |
3643 | op0 = simplify_unary_operation (NEG, mode, op0, mode); |
3644 | else | |
3645 | op0 = expand_unop (mode, neg_optab, op0, target, 0); | |
3646 | if (op0 != target) | |
3647 | emit_move_insn (target, op0); | |
3648 | ||
3649 | emit_label (label); | |
3650 | ||
3651 | return target; | |
3652 | } | |
3653 | ||
3654 | ||
3655 | /* A subroutine of expand_copysign, perform the entire copysign operation | |
3656 | with integer bitmasks. BITPOS is the position of the sign bit; OP0_IS_ABS | |
3657 | is true if op0 is known to have its sign bit clear. */ | |
3658 | ||
3659 | static rtx | |
3660 | expand_copysign_bit (enum machine_mode mode, rtx op0, rtx op1, rtx target, | |
3661 | int bitpos, bool op0_is_abs) | |
3662 | { | |
3663 | enum machine_mode imode; | |
ae394659 RH |
3664 | int word, nwords, i; |
3665 | rtx temp, insns; | |
046625fa | 3666 | |
8c55a142 | 3667 | if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) |
046625fa | 3668 | { |
8c55a142 RH |
3669 | imode = int_mode_for_mode (mode); |
3670 | if (imode == BLKmode) | |
3671 | return NULL_RTX; | |
3672 | word = 0; | |
3673 | nwords = 1; | |
3674 | } | |
3675 | else | |
3676 | { | |
3677 | imode = word_mode; | |
3678 | ||
3679 | if (FLOAT_WORDS_BIG_ENDIAN) | |
3680 | word = (GET_MODE_BITSIZE (mode) - bitpos) / BITS_PER_WORD; | |
3681 | else | |
3682 | word = bitpos / BITS_PER_WORD; | |
3683 | bitpos = bitpos % BITS_PER_WORD; | |
3684 | nwords = (GET_MODE_BITSIZE (mode) + BITS_PER_WORD - 1) / BITS_PER_WORD; | |
046625fa RH |
3685 | } |
3686 | ||
807e902e | 3687 | wide_int mask = wi::set_bit_in_zero (bitpos, GET_MODE_PRECISION (imode)); |
046625fa | 3688 | |
02972eaf RS |
3689 | if (target == 0 |
3690 | || target == op0 | |
3691 | || target == op1 | |
3692 | || (nwords > 1 && !valid_multiword_target_p (target))) | |
8c55a142 RH |
3693 | target = gen_reg_rtx (mode); |
3694 | ||
3695 | if (nwords > 1) | |
046625fa | 3696 | { |
8c55a142 RH |
3697 | start_sequence (); |
3698 | ||
3699 | for (i = 0; i < nwords; ++i) | |
046625fa | 3700 | { |
8c55a142 RH |
3701 | rtx targ_piece = operand_subword (target, i, 1, mode); |
3702 | rtx op0_piece = operand_subword_force (op0, i, mode); | |
c414ac1d | 3703 | |
8c55a142 RH |
3704 | if (i == word) |
3705 | { | |
ae394659 | 3706 | if (!op0_is_abs) |
54fb1ae0 AS |
3707 | op0_piece |
3708 | = expand_binop (imode, and_optab, op0_piece, | |
807e902e | 3709 | immed_wide_int_const (~mask, imode), |
54fb1ae0 | 3710 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
8c55a142 RH |
3711 | op1 = expand_binop (imode, and_optab, |
3712 | operand_subword_force (op1, i, mode), | |
807e902e | 3713 | immed_wide_int_const (mask, imode), |
8c55a142 RH |
3714 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3715 | ||
3716 | temp = expand_binop (imode, ior_optab, op0_piece, op1, | |
3717 | targ_piece, 1, OPTAB_LIB_WIDEN); | |
3718 | if (temp != targ_piece) | |
3719 | emit_move_insn (targ_piece, temp); | |
3720 | } | |
3721 | else | |
3722 | emit_move_insn (targ_piece, op0_piece); | |
046625fa | 3723 | } |
8c55a142 RH |
3724 | |
3725 | insns = get_insns (); | |
3726 | end_sequence (); | |
3727 | ||
d70dcf29 | 3728 | emit_insn (insns); |
046625fa RH |
3729 | } |
3730 | else | |
8c55a142 RH |
3731 | { |
3732 | op1 = expand_binop (imode, and_optab, gen_lowpart (imode, op1), | |
807e902e | 3733 | immed_wide_int_const (mask, imode), |
8c55a142 RH |
3734 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3735 | ||
3736 | op0 = gen_lowpart (imode, op0); | |
ae394659 | 3737 | if (!op0_is_abs) |
8c55a142 | 3738 | op0 = expand_binop (imode, and_optab, op0, |
807e902e | 3739 | immed_wide_int_const (~mask, imode), |
8c55a142 RH |
3740 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
3741 | ||
3742 | temp = expand_binop (imode, ior_optab, op0, op1, | |
3743 | gen_lowpart (imode, target), 1, OPTAB_LIB_WIDEN); | |
3744 | target = lowpart_subreg_maybe_copy (mode, temp, imode); | |
3745 | } | |
046625fa RH |
3746 | |
3747 | return target; | |
3748 | } | |
ae394659 | 3749 | |
c414ac1d | 3750 | /* Expand the C99 copysign operation. OP0 and OP1 must be the same |
ae394659 RH |
3751 | scalar floating point mode. Return NULL if we do not know how to |
3752 | expand the operation inline. */ | |
3753 | ||
3754 | rtx | |
3755 | expand_copysign (rtx op0, rtx op1, rtx target) | |
3756 | { | |
3757 | enum machine_mode mode = GET_MODE (op0); | |
3758 | const struct real_format *fmt; | |
ae394659 RH |
3759 | bool op0_is_abs; |
3760 | rtx temp; | |
3761 | ||
3762 | gcc_assert (SCALAR_FLOAT_MODE_P (mode)); | |
3763 | gcc_assert (GET_MODE (op1) == mode); | |
3764 | ||
3765 | /* First try to do it with a special instruction. */ | |
3766 | temp = expand_binop (mode, copysign_optab, op0, op1, | |
3767 | target, 0, OPTAB_DIRECT); | |
3768 | if (temp) | |
3769 | return temp; | |
3770 | ||
3771 | fmt = REAL_MODE_FORMAT (mode); | |
3772 | if (fmt == NULL || !fmt->has_signed_zero) | |
3773 | return NULL_RTX; | |
3774 | ||
ae394659 | 3775 | op0_is_abs = false; |
48175537 | 3776 | if (CONST_DOUBLE_AS_FLOAT_P (op0)) |
ae394659 RH |
3777 | { |
3778 | if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) | |
3779 | op0 = simplify_unary_operation (ABS, mode, op0, mode); | |
3780 | op0_is_abs = true; | |
3781 | } | |
3782 | ||
c064fde5 | 3783 | if (fmt->signbit_ro >= 0 |
48175537 | 3784 | && (CONST_DOUBLE_AS_FLOAT_P (op0) |
947131ba RS |
3785 | || (optab_handler (neg_optab, mode) != CODE_FOR_nothing |
3786 | && optab_handler (abs_optab, mode) != CODE_FOR_nothing))) | |
ae394659 RH |
3787 | { |
3788 | temp = expand_copysign_absneg (mode, op0, op1, target, | |
c064fde5 | 3789 | fmt->signbit_ro, op0_is_abs); |
ae394659 RH |
3790 | if (temp) |
3791 | return temp; | |
3792 | } | |
3793 | ||
c064fde5 RS |
3794 | if (fmt->signbit_rw < 0) |
3795 | return NULL_RTX; | |
3796 | return expand_copysign_bit (mode, op0, op1, target, | |
3797 | fmt->signbit_rw, op0_is_abs); | |
ae394659 | 3798 | } |
7fd01431 | 3799 | \f |
77c9c6c2 RK |
3800 | /* Generate an instruction whose insn-code is INSN_CODE, |
3801 | with two operands: an output TARGET and an input OP0. | |
3802 | TARGET *must* be nonzero, and the output is always stored there. | |
3803 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
b8698a0f | 3804 | the value that is stored into TARGET. |
77c9c6c2 | 3805 | |
18bd082d JH |
3806 | Return false if expansion failed. */ |
3807 | ||
3808 | bool | |
a5c7d693 RS |
3809 | maybe_emit_unop_insn (enum insn_code icode, rtx target, rtx op0, |
3810 | enum rtx_code code) | |
77c9c6c2 | 3811 | { |
a5c7d693 | 3812 | struct expand_operand ops[2]; |
77c9c6c2 | 3813 | rtx pat; |
77c9c6c2 | 3814 | |
a5c7d693 RS |
3815 | create_output_operand (&ops[0], target, GET_MODE (target)); |
3816 | create_input_operand (&ops[1], op0, GET_MODE (op0)); | |
3817 | pat = maybe_gen_insn (icode, 2, ops); | |
18bd082d | 3818 | if (!pat) |
a5c7d693 | 3819 | return false; |
77c9c6c2 | 3820 | |
2f937369 | 3821 | if (INSN_P (pat) && NEXT_INSN (pat) != NULL_RTX && code != UNKNOWN) |
a5c7d693 | 3822 | add_equal_note (pat, ops[0].value, code, ops[1].value, NULL_RTX); |
0c20a65f | 3823 | |
77c9c6c2 RK |
3824 | emit_insn (pat); |
3825 | ||
a5c7d693 RS |
3826 | if (ops[0].value != target) |
3827 | emit_move_insn (target, ops[0].value); | |
18bd082d JH |
3828 | return true; |
3829 | } | |
3830 | /* Generate an instruction whose insn-code is INSN_CODE, | |
3831 | with two operands: an output TARGET and an input OP0. | |
3832 | TARGET *must* be nonzero, and the output is always stored there. | |
3833 | CODE is an rtx code such that (CODE OP0) is an rtx that describes | |
3834 | the value that is stored into TARGET. */ | |
3835 | ||
3836 | void | |
a5c7d693 | 3837 | emit_unop_insn (enum insn_code icode, rtx target, rtx op0, enum rtx_code code) |
18bd082d JH |
3838 | { |
3839 | bool ok = maybe_emit_unop_insn (icode, target, op0, code); | |
3840 | gcc_assert (ok); | |
77c9c6c2 RK |
3841 | } |
3842 | \f | |
326a31e9 R |
3843 | struct no_conflict_data |
3844 | { | |
3845 | rtx target, first, insn; | |
3846 | bool must_stay; | |
3847 | }; | |
3848 | ||
d70dcf29 KZ |
3849 | /* Called via note_stores by emit_libcall_block. Set P->must_stay if |
3850 | the currently examined clobber / store has to stay in the list of | |
3851 | insns that constitute the actual libcall block. */ | |
326a31e9 | 3852 | static void |
7bc980e1 | 3853 | no_conflict_move_test (rtx dest, const_rtx set, void *p0) |
326a31e9 | 3854 | { |
d3bfe4de | 3855 | struct no_conflict_data *p= (struct no_conflict_data *) p0; |
326a31e9 R |
3856 | |
3857 | /* If this inns directly contributes to setting the target, it must stay. */ | |
3858 | if (reg_overlap_mentioned_p (p->target, dest)) | |
3859 | p->must_stay = true; | |
3860 | /* If we haven't committed to keeping any other insns in the list yet, | |
3861 | there is nothing more to check. */ | |
3862 | else if (p->insn == p->first) | |
3863 | return; | |
3864 | /* If this insn sets / clobbers a register that feeds one of the insns | |
3865 | already in the list, this insn has to stay too. */ | |
9617ccfd R |
3866 | else if (reg_overlap_mentioned_p (dest, PATTERN (p->first)) |
3867 | || (CALL_P (p->first) && (find_reg_fusage (p->first, USE, dest))) | |
326a31e9 R |
3868 | || reg_used_between_p (dest, p->first, p->insn) |
3869 | /* Likewise if this insn depends on a register set by a previous | |
ca7a5aec R |
3870 | insn in the list, or if it sets a result (presumably a hard |
3871 | register) that is set or clobbered by a previous insn. | |
3872 | N.B. the modified_*_p (SET_DEST...) tests applied to a MEM | |
3873 | SET_DEST perform the former check on the address, and the latter | |
3874 | check on the MEM. */ | |
326a31e9 R |
3875 | || (GET_CODE (set) == SET |
3876 | && (modified_in_p (SET_SRC (set), p->first) | |
ca7a5aec R |
3877 | || modified_in_p (SET_DEST (set), p->first) |
3878 | || modified_between_p (SET_SRC (set), p->first, p->insn) | |
3879 | || modified_between_p (SET_DEST (set), p->first, p->insn)))) | |
326a31e9 R |
3880 | p->must_stay = true; |
3881 | } | |
3882 | ||
77c9c6c2 RK |
3883 | \f |
3884 | /* Emit code to make a call to a constant function or a library call. | |
3885 | ||
3886 | INSNS is a list containing all insns emitted in the call. | |
3887 | These insns leave the result in RESULT. Our block is to copy RESULT | |
3888 | to TARGET, which is logically equivalent to EQUIV. | |
3889 | ||
3890 | We first emit any insns that set a pseudo on the assumption that these are | |
3891 | loading constants into registers; doing so allows them to be safely cse'ed | |
3892 | between blocks. Then we emit all the other insns in the block, followed by | |
3893 | an insn to move RESULT to TARGET. This last insn will have a REQ_EQUAL | |
856905c2 SB |
3894 | note with an operand of EQUIV. */ |
3895 | ||
b55f62cc RG |
3896 | static void |
3897 | emit_libcall_block_1 (rtx insns, rtx target, rtx result, rtx equiv, | |
3898 | bool equiv_may_trap) | |
77c9c6c2 | 3899 | { |
aff2c2d3 | 3900 | rtx final_dest = target; |
0f900dfa | 3901 | rtx next, last, insn; |
77c9c6c2 | 3902 | |
aff2c2d3 BS |
3903 | /* If this is a reg with REG_USERVAR_P set, then it could possibly turn |
3904 | into a MEM later. Protect the libcall block from this change. */ | |
3905 | if (! REG_P (target) || REG_USERVAR_P (target)) | |
3906 | target = gen_reg_rtx (GET_MODE (target)); | |
0c20a65f | 3907 | |
5154e79a AH |
3908 | /* If we're using non-call exceptions, a libcall corresponding to an |
3909 | operation that may trap may also trap. */ | |
1d65f45c | 3910 | /* ??? See the comment in front of make_reg_eh_region_note. */ |
b55f62cc RG |
3911 | if (cfun->can_throw_non_call_exceptions |
3912 | && (equiv_may_trap || may_trap_p (equiv))) | |
5154e79a AH |
3913 | { |
3914 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
4b4bf941 | 3915 | if (CALL_P (insn)) |
5154e79a AH |
3916 | { |
3917 | rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); | |
1d65f45c RH |
3918 | if (note) |
3919 | { | |
3920 | int lp_nr = INTVAL (XEXP (note, 0)); | |
3921 | if (lp_nr == 0 || lp_nr == INT_MIN) | |
3922 | remove_note (insn, note); | |
3923 | } | |
5154e79a AH |
3924 | } |
3925 | } | |
3926 | else | |
1d65f45c RH |
3927 | { |
3928 | /* Look for any CALL_INSNs in this sequence, and attach a REG_EH_REGION | |
3929 | reg note to indicate that this call cannot throw or execute a nonlocal | |
3930 | goto (unless there is already a REG_EH_REGION note, in which case | |
3931 | we update it). */ | |
3932 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
3933 | if (CALL_P (insn)) | |
3934 | make_reg_eh_region_note_nothrow_nononlocal (insn); | |
3935 | } | |
b472794d | 3936 | |
77c9c6c2 | 3937 | /* First emit all insns that set pseudos. Remove them from the list as |
ccf5f342 | 3938 | we go. Avoid insns that set pseudos which were referenced in previous |
29ebe69a | 3939 | insns. These can be generated by move_by_pieces, for example, |
ccf5f342 RK |
3940 | to update an address. Similarly, avoid insns that reference things |
3941 | set in previous insns. */ | |
77c9c6c2 RK |
3942 | |
3943 | for (insn = insns; insn; insn = next) | |
3944 | { | |
3945 | rtx set = single_set (insn); | |
3946 | ||
3947 | next = NEXT_INSN (insn); | |
3948 | ||
f8cfc6aa | 3949 | if (set != 0 && REG_P (SET_DEST (set)) |
748ebfc7 | 3950 | && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) |
77c9c6c2 | 3951 | { |
748ebfc7 R |
3952 | struct no_conflict_data data; |
3953 | ||
3954 | data.target = const0_rtx; | |
3955 | data.first = insns; | |
3956 | data.insn = insn; | |
3957 | data.must_stay = 0; | |
3958 | note_stores (PATTERN (insn), no_conflict_move_test, &data); | |
3959 | if (! data.must_stay) | |
3960 | { | |
3961 | if (PREV_INSN (insn)) | |
3962 | NEXT_INSN (PREV_INSN (insn)) = next; | |
3963 | else | |
3964 | insns = next; | |
77c9c6c2 | 3965 | |
748ebfc7 R |
3966 | if (next) |
3967 | PREV_INSN (next) = PREV_INSN (insn); | |
77c9c6c2 | 3968 | |
748ebfc7 R |
3969 | add_insn (insn); |
3970 | } | |
77c9c6c2 | 3971 | } |
695a94b3 RS |
3972 | |
3973 | /* Some ports use a loop to copy large arguments onto the stack. | |
3974 | Don't move anything outside such a loop. */ | |
4b4bf941 | 3975 | if (LABEL_P (insn)) |
695a94b3 | 3976 | break; |
77c9c6c2 RK |
3977 | } |
3978 | ||
77c9c6c2 | 3979 | /* Write the remaining insns followed by the final copy. */ |
77c9c6c2 RK |
3980 | for (insn = insns; insn; insn = next) |
3981 | { | |
3982 | next = NEXT_INSN (insn); | |
3983 | ||
3984 | add_insn (insn); | |
3985 | } | |
3986 | ||
3987 | last = emit_move_insn (target, result); | |
7543f918 | 3988 | set_dst_reg_note (last, REG_EQUAL, copy_rtx (equiv), target); |
77c9c6c2 | 3989 | |
e85427f9 BS |
3990 | if (final_dest != target) |
3991 | emit_move_insn (final_dest, target); | |
77c9c6c2 | 3992 | } |
b55f62cc RG |
3993 | |
3994 | void | |
3995 | emit_libcall_block (rtx insns, rtx target, rtx result, rtx equiv) | |
3996 | { | |
3997 | emit_libcall_block_1 (insns, target, result, equiv, false); | |
3998 | } | |
77c9c6c2 | 3999 | \f |
1c0290ea | 4000 | /* Nonzero if we can perform a comparison of mode MODE straightforwardly. |
1eb8759b RH |
4001 | PURPOSE describes how this comparison will be used. CODE is the rtx |
4002 | comparison code we will be using. | |
4003 | ||
4004 | ??? Actually, CODE is slightly weaker than that. A target is still | |
0c20a65f | 4005 | required to implement all of the normal bcc operations, but not |
1eb8759b | 4006 | required to implement all (or any) of the unordered bcc operations. */ |
0c20a65f | 4007 | |
1c0290ea | 4008 | int |
0c20a65f AJ |
4009 | can_compare_p (enum rtx_code code, enum machine_mode mode, |
4010 | enum can_compare_purpose purpose) | |
b30f05db | 4011 | { |
c3c64f50 PB |
4012 | rtx test; |
4013 | test = gen_rtx_fmt_ee (code, mode, const0_rtx, const0_rtx); | |
b30f05db BS |
4014 | do |
4015 | { | |
2ef6ce06 | 4016 | enum insn_code icode; |
c3c64f50 | 4017 | |
1c0290ea | 4018 | if (purpose == ccp_jump |
947131ba | 4019 | && (icode = optab_handler (cbranch_optab, mode)) != CODE_FOR_nothing |
2ef6ce06 | 4020 | && insn_operand_matches (icode, 0, test)) |
c3c64f50 PB |
4021 | return 1; |
4022 | if (purpose == ccp_store_flag | |
947131ba | 4023 | && (icode = optab_handler (cstore_optab, mode)) != CODE_FOR_nothing |
2ef6ce06 | 4024 | && insn_operand_matches (icode, 1, test)) |
c3c64f50 | 4025 | return 1; |
1c0290ea | 4026 | if (purpose == ccp_cmov |
947131ba | 4027 | && optab_handler (cmov_optab, mode) != CODE_FOR_nothing) |
1c0290ea | 4028 | return 1; |
c3c64f50 | 4029 | |
b30f05db | 4030 | mode = GET_MODE_WIDER_MODE (mode); |
c3c64f50 | 4031 | PUT_MODE (test, mode); |
1c0290ea BS |
4032 | } |
4033 | while (mode != VOIDmode); | |
b30f05db BS |
4034 | |
4035 | return 0; | |
4036 | } | |
4037 | ||
4038 | /* This function is called when we are going to emit a compare instruction that | |
4039 | compares the values found in *PX and *PY, using the rtl operator COMPARISON. | |
4040 | ||
4041 | *PMODE is the mode of the inputs (in case they are const_int). | |
4042 | *PUNSIGNEDP nonzero says that the operands are unsigned; | |
f90b7a5a | 4043 | this matters if they need to be widened (as given by METHODS). |
77c9c6c2 | 4044 | |
a06ef755 | 4045 | If they have mode BLKmode, then SIZE specifies the size of both operands. |
77c9c6c2 | 4046 | |
b30f05db BS |
4047 | This function performs all the setup necessary so that the caller only has |
4048 | to emit a single comparison insn. This setup can involve doing a BLKmode | |
4049 | comparison or emitting a library call to perform the comparison if no insn | |
4050 | is available to handle it. | |
4051 | The values which are passed in through pointers can be modified; the caller | |
0e61db61 NS |
4052 | should perform the comparison on the modified values. Constant |
4053 | comparisons must have already been folded. */ | |
77c9c6c2 | 4054 | |
a06ef755 | 4055 | static void |
f90b7a5a PB |
4056 | prepare_cmp_insn (rtx x, rtx y, enum rtx_code comparison, rtx size, |
4057 | int unsignedp, enum optab_methods methods, | |
4058 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 4059 | { |
b30f05db | 4060 | enum machine_mode mode = *pmode; |
f90b7a5a PB |
4061 | rtx libfunc, test; |
4062 | enum machine_mode cmp_mode; | |
4063 | enum mode_class mclass; | |
4064 | ||
4065 | /* The other methods are not needed. */ | |
4066 | gcc_assert (methods == OPTAB_DIRECT || methods == OPTAB_WIDEN | |
4067 | || methods == OPTAB_LIB_WIDEN); | |
77c9c6c2 | 4068 | |
5e8d1826 PB |
4069 | /* If we are optimizing, force expensive constants into a register. */ |
4070 | if (CONSTANT_P (x) && optimize | |
68f932c4 | 4071 | && (rtx_cost (x, COMPARE, 0, optimize_insn_for_speed_p ()) |
5e8d1826 PB |
4072 | > COSTS_N_INSNS (1))) |
4073 | x = force_reg (mode, x); | |
4074 | ||
4075 | if (CONSTANT_P (y) && optimize | |
68f932c4 | 4076 | && (rtx_cost (y, COMPARE, 1, optimize_insn_for_speed_p ()) |
5e8d1826 PB |
4077 | > COSTS_N_INSNS (1))) |
4078 | y = force_reg (mode, y); | |
4079 | ||
362cc3d4 | 4080 | #ifdef HAVE_cc0 |
0e61db61 NS |
4081 | /* Make sure if we have a canonical comparison. The RTL |
4082 | documentation states that canonical comparisons are required only | |
4083 | for targets which have cc0. */ | |
e3feb571 | 4084 | gcc_assert (!CONSTANT_P (x) || CONSTANT_P (y)); |
362cc3d4 MH |
4085 | #endif |
4086 | ||
77c9c6c2 RK |
4087 | /* Don't let both operands fail to indicate the mode. */ |
4088 | if (GET_MODE (x) == VOIDmode && GET_MODE (y) == VOIDmode) | |
4089 | x = force_reg (mode, x); | |
f90b7a5a PB |
4090 | if (mode == VOIDmode) |
4091 | mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : GET_MODE (y); | |
77c9c6c2 RK |
4092 | |
4093 | /* Handle all BLKmode compares. */ | |
4094 | ||
4095 | if (mode == BLKmode) | |
4096 | { | |
f90b7a5a | 4097 | enum machine_mode result_mode; |
118355a0 ZW |
4098 | enum insn_code cmp_code; |
4099 | tree length_type; | |
4100 | rtx libfunc; | |
b30f05db | 4101 | rtx result; |
118355a0 | 4102 | rtx opalign |
f4dc10d1 | 4103 | = GEN_INT (MIN (MEM_ALIGN (x), MEM_ALIGN (y)) / BITS_PER_UNIT); |
b30f05db | 4104 | |
e3feb571 | 4105 | gcc_assert (size); |
118355a0 | 4106 | |
118355a0 ZW |
4107 | /* Try to use a memory block compare insn - either cmpstr |
4108 | or cmpmem will do. */ | |
4109 | for (cmp_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); | |
4110 | cmp_mode != VOIDmode; | |
4111 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode)) | |
358b8f01 | 4112 | { |
f9621cc4 | 4113 | cmp_code = direct_optab_handler (cmpmem_optab, cmp_mode); |
118355a0 | 4114 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 4115 | cmp_code = direct_optab_handler (cmpstr_optab, cmp_mode); |
40c1d5f8 | 4116 | if (cmp_code == CODE_FOR_nothing) |
f9621cc4 | 4117 | cmp_code = direct_optab_handler (cmpstrn_optab, cmp_mode); |
118355a0 ZW |
4118 | if (cmp_code == CODE_FOR_nothing) |
4119 | continue; | |
4120 | ||
4121 | /* Must make sure the size fits the insn's mode. */ | |
481683e1 | 4122 | if ((CONST_INT_P (size) |
118355a0 ZW |
4123 | && INTVAL (size) >= (1 << GET_MODE_BITSIZE (cmp_mode))) |
4124 | || (GET_MODE_BITSIZE (GET_MODE (size)) | |
4125 | > GET_MODE_BITSIZE (cmp_mode))) | |
4126 | continue; | |
4127 | ||
4128 | result_mode = insn_data[cmp_code].operand[0].mode; | |
358b8f01 | 4129 | result = gen_reg_rtx (result_mode); |
118355a0 ZW |
4130 | size = convert_to_mode (cmp_mode, size, 1); |
4131 | emit_insn (GEN_FCN (cmp_code) (result, x, y, size, opalign)); | |
4132 | ||
f90b7a5a PB |
4133 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, result, const0_rtx); |
4134 | *pmode = result_mode; | |
118355a0 | 4135 | return; |
77c9c6c2 | 4136 | } |
118355a0 | 4137 | |
f90b7a5a PB |
4138 | if (methods != OPTAB_LIB && methods != OPTAB_LIB_WIDEN) |
4139 | goto fail; | |
4140 | ||
8f99553f | 4141 | /* Otherwise call a library function, memcmp. */ |
118355a0 ZW |
4142 | libfunc = memcmp_libfunc; |
4143 | length_type = sizetype; | |
118355a0 ZW |
4144 | result_mode = TYPE_MODE (integer_type_node); |
4145 | cmp_mode = TYPE_MODE (length_type); | |
4146 | size = convert_to_mode (TYPE_MODE (length_type), size, | |
8df83eae | 4147 | TYPE_UNSIGNED (length_type)); |
118355a0 | 4148 | |
84b8030f | 4149 | result = emit_library_call_value (libfunc, 0, LCT_PURE, |
118355a0 ZW |
4150 | result_mode, 3, |
4151 | XEXP (x, 0), Pmode, | |
4152 | XEXP (y, 0), Pmode, | |
4153 | size, cmp_mode); | |
ae5f0678 UB |
4154 | x = result; |
4155 | y = const0_rtx; | |
4156 | mode = result_mode; | |
4157 | methods = OPTAB_LIB_WIDEN; | |
4158 | unsignedp = false; | |
77c9c6c2 RK |
4159 | } |
4160 | ||
27ab3e91 RH |
4161 | /* Don't allow operands to the compare to trap, as that can put the |
4162 | compare and branch in different basic blocks. */ | |
8f4f502f | 4163 | if (cfun->can_throw_non_call_exceptions) |
27ab3e91 RH |
4164 | { |
4165 | if (may_trap_p (x)) | |
4166 | x = force_reg (mode, x); | |
4167 | if (may_trap_p (y)) | |
4168 | y = force_reg (mode, y); | |
4169 | } | |
4170 | ||
4a77c72b PB |
4171 | if (GET_MODE_CLASS (mode) == MODE_CC) |
4172 | { | |
f90b7a5a PB |
4173 | gcc_assert (can_compare_p (comparison, CCmode, ccp_jump)); |
4174 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4a77c72b PB |
4175 | return; |
4176 | } | |
77c9c6c2 | 4177 | |
f90b7a5a PB |
4178 | mclass = GET_MODE_CLASS (mode); |
4179 | test = gen_rtx_fmt_ee (comparison, VOIDmode, x, y); | |
4180 | cmp_mode = mode; | |
4181 | do | |
4182 | { | |
4183 | enum insn_code icode; | |
947131ba | 4184 | icode = optab_handler (cbranch_optab, cmp_mode); |
f90b7a5a | 4185 | if (icode != CODE_FOR_nothing |
2ef6ce06 | 4186 | && insn_operand_matches (icode, 0, test)) |
f90b7a5a PB |
4187 | { |
4188 | rtx last = get_last_insn (); | |
4189 | rtx op0 = prepare_operand (icode, x, 1, mode, cmp_mode, unsignedp); | |
4190 | rtx op1 = prepare_operand (icode, y, 2, mode, cmp_mode, unsignedp); | |
4191 | if (op0 && op1 | |
2ef6ce06 RS |
4192 | && insn_operand_matches (icode, 1, op0) |
4193 | && insn_operand_matches (icode, 2, op1)) | |
f90b7a5a PB |
4194 | { |
4195 | XEXP (test, 0) = op0; | |
4196 | XEXP (test, 1) = op1; | |
4197 | *ptest = test; | |
4198 | *pmode = cmp_mode; | |
4199 | return; | |
4200 | } | |
4201 | delete_insns_since (last); | |
4202 | } | |
4203 | ||
4204 | if (methods == OPTAB_DIRECT || !CLASS_HAS_WIDER_MODES_P (mclass)) | |
4205 | break; | |
4206 | cmp_mode = GET_MODE_WIDER_MODE (cmp_mode); | |
4207 | } | |
4208 | while (cmp_mode != VOIDmode); | |
4209 | ||
4210 | if (methods != OPTAB_LIB_WIDEN) | |
4211 | goto fail; | |
4212 | ||
4213 | if (!SCALAR_FLOAT_MODE_P (mode)) | |
77c9c6c2 | 4214 | { |
9725066d | 4215 | rtx result; |
0a81f074 | 4216 | enum machine_mode ret_mode; |
9725066d | 4217 | |
f90b7a5a PB |
4218 | /* Handle a libcall just for the mode we are using. */ |
4219 | libfunc = optab_libfunc (cmp_optab, mode); | |
4220 | gcc_assert (libfunc); | |
4221 | ||
77c9c6c2 RK |
4222 | /* If we want unsigned, and this mode has a distinct unsigned |
4223 | comparison routine, use that. */ | |
8a33f100 JH |
4224 | if (unsignedp) |
4225 | { | |
ba8a73e9 EB |
4226 | rtx ulibfunc = optab_libfunc (ucmp_optab, mode); |
4227 | if (ulibfunc) | |
4228 | libfunc = ulibfunc; | |
8a33f100 | 4229 | } |
77c9c6c2 | 4230 | |
0a81f074 | 4231 | ret_mode = targetm.libgcc_cmp_return_mode (); |
84b8030f | 4232 | result = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
0a81f074 | 4233 | ret_mode, 2, x, mode, y, mode); |
9725066d | 4234 | |
f34312c2 CD |
4235 | /* There are two kinds of comparison routines. Biased routines |
4236 | return 0/1/2, and unbiased routines return -1/0/1. Other parts | |
4237 | of gcc expect that the comparison operation is equivalent | |
b8698a0f | 4238 | to the modified comparison. For signed comparisons compare the |
f34312c2 CD |
4239 | result against 1 in the biased case, and zero in the unbiased |
4240 | case. For unsigned comparisons always compare against 1 after | |
917f1b7e | 4241 | biasing the unbiased result by adding 1. This gives us a way to |
f64398b5 JB |
4242 | represent LTU. |
4243 | The comparisons in the fixed-point helper library are always | |
4244 | biased. */ | |
f90b7a5a PB |
4245 | x = result; |
4246 | y = const1_rtx; | |
f34312c2 | 4247 | |
f64398b5 | 4248 | if (!TARGET_LIB_INT_CMP_BIASED && !ALL_FIXED_POINT_MODE_P (mode)) |
b3f8d95d | 4249 | { |
f90b7a5a | 4250 | if (unsignedp) |
0a81f074 | 4251 | x = plus_constant (ret_mode, result, 1); |
f34312c2 | 4252 | else |
f90b7a5a | 4253 | y = const0_rtx; |
b3f8d95d | 4254 | } |
f90b7a5a PB |
4255 | |
4256 | *pmode = word_mode; | |
4257 | prepare_cmp_insn (x, y, comparison, NULL_RTX, unsignedp, methods, | |
4258 | ptest, pmode); | |
77c9c6c2 | 4259 | } |
b8698a0f | 4260 | else |
f90b7a5a | 4261 | prepare_float_lib_cmp (x, y, comparison, ptest, pmode); |
77c9c6c2 | 4262 | |
f90b7a5a PB |
4263 | return; |
4264 | ||
4265 | fail: | |
4266 | *ptest = NULL_RTX; | |
77c9c6c2 RK |
4267 | } |
4268 | ||
b30f05db BS |
4269 | /* Before emitting an insn with code ICODE, make sure that X, which is going |
4270 | to be used for operand OPNUM of the insn, is converted from mode MODE to | |
4fe9b91c | 4271 | WIDER_MODE (UNSIGNEDP determines whether it is an unsigned conversion), and |
b30f05db | 4272 | that it is accepted by the operand predicate. Return the new value. */ |
749a2da1 | 4273 | |
f90b7a5a | 4274 | rtx |
2ef6ce06 | 4275 | prepare_operand (enum insn_code icode, rtx x, int opnum, enum machine_mode mode, |
0c20a65f | 4276 | enum machine_mode wider_mode, int unsignedp) |
b30f05db | 4277 | { |
b30f05db BS |
4278 | if (mode != wider_mode) |
4279 | x = convert_modes (wider_mode, mode, x, unsignedp); | |
4280 | ||
2ef6ce06 | 4281 | if (!insn_operand_matches (icode, opnum, x)) |
d893ccde | 4282 | { |
ef4375b2 | 4283 | if (reload_completed) |
d893ccde | 4284 | return NULL_RTX; |
2ef6ce06 | 4285 | x = copy_to_mode_reg (insn_data[(int) icode].operand[opnum].mode, x); |
d893ccde RH |
4286 | } |
4287 | ||
b30f05db BS |
4288 | return x; |
4289 | } | |
4290 | ||
4291 | /* Subroutine of emit_cmp_and_jump_insns; this function is called when we know | |
f90b7a5a | 4292 | we can do the branch. */ |
b30f05db BS |
4293 | |
4294 | static void | |
a4da41e1 | 4295 | emit_cmp_and_jump_insn_1 (rtx test, enum machine_mode mode, rtx label, int prob) |
b30f05db | 4296 | { |
f90b7a5a PB |
4297 | enum machine_mode optab_mode; |
4298 | enum mode_class mclass; | |
4299 | enum insn_code icode; | |
a4da41e1 | 4300 | rtx insn; |
b30f05db | 4301 | |
f90b7a5a PB |
4302 | mclass = GET_MODE_CLASS (mode); |
4303 | optab_mode = (mclass == MODE_CC) ? CCmode : mode; | |
947131ba | 4304 | icode = optab_handler (cbranch_optab, optab_mode); |
8127d0e0 | 4305 | |
f90b7a5a | 4306 | gcc_assert (icode != CODE_FOR_nothing); |
2ef6ce06 | 4307 | gcc_assert (insn_operand_matches (icode, 0, test)); |
a4da41e1 ER |
4308 | insn = emit_jump_insn (GEN_FCN (icode) (test, XEXP (test, 0), |
4309 | XEXP (test, 1), label)); | |
4310 | if (prob != -1 | |
0a6a6ac9 | 4311 | && profile_status_for_fn (cfun) != PROFILE_ABSENT |
a4da41e1 ER |
4312 | && insn |
4313 | && JUMP_P (insn) | |
0f379f76 ER |
4314 | && any_condjump_p (insn) |
4315 | && !find_reg_note (insn, REG_BR_PROB, 0)) | |
e5af9ddd | 4316 | add_int_reg_note (insn, REG_BR_PROB, prob); |
b30f05db BS |
4317 | } |
4318 | ||
362cc3d4 MH |
4319 | /* Generate code to compare X with Y so that the condition codes are |
4320 | set and to jump to LABEL if the condition is true. If X is a | |
4321 | constant and Y is not a constant, then the comparison is swapped to | |
4322 | ensure that the comparison RTL has the canonical form. | |
4323 | ||
c5d5d461 | 4324 | UNSIGNEDP nonzero says that X and Y are unsigned; this matters if they |
f90b7a5a PB |
4325 | need to be widened. UNSIGNEDP is also used to select the proper |
4326 | branch condition code. | |
362cc3d4 | 4327 | |
a06ef755 | 4328 | If X and Y have mode BLKmode, then SIZE specifies the size of both X and Y. |
362cc3d4 | 4329 | |
c5d5d461 JL |
4330 | MODE is the mode of the inputs (in case they are const_int). |
4331 | ||
f90b7a5a PB |
4332 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). |
4333 | It will be potentially converted into an unsigned variant based on | |
a4da41e1 ER |
4334 | UNSIGNEDP to select a proper jump instruction. |
4335 | ||
4336 | PROB is the probability of jumping to LABEL. */ | |
362cc3d4 MH |
4337 | |
4338 | void | |
0c20a65f | 4339 | emit_cmp_and_jump_insns (rtx x, rtx y, enum rtx_code comparison, rtx size, |
a4da41e1 ER |
4340 | enum machine_mode mode, int unsignedp, rtx label, |
4341 | int prob) | |
362cc3d4 | 4342 | { |
8c9864f3 | 4343 | rtx op0 = x, op1 = y; |
f90b7a5a | 4344 | rtx test; |
8c9864f3 JH |
4345 | |
4346 | /* Swap operands and condition to ensure canonical RTL. */ | |
45475a3f PB |
4347 | if (swap_commutative_operands_p (x, y) |
4348 | && can_compare_p (swap_condition (comparison), mode, ccp_jump)) | |
362cc3d4 | 4349 | { |
8c9864f3 JH |
4350 | op0 = y, op1 = x; |
4351 | comparison = swap_condition (comparison); | |
362cc3d4 | 4352 | } |
0ca40216 | 4353 | |
45475a3f PB |
4354 | /* If OP0 is still a constant, then both X and Y must be constants |
4355 | or the opposite comparison is not supported. Force X into a register | |
4356 | to create canonical RTL. */ | |
0ca40216 JL |
4357 | if (CONSTANT_P (op0)) |
4358 | op0 = force_reg (mode, op0); | |
0ca40216 | 4359 | |
c5d5d461 JL |
4360 | if (unsignedp) |
4361 | comparison = unsigned_condition (comparison); | |
a06ef755 | 4362 | |
f90b7a5a PB |
4363 | prepare_cmp_insn (op0, op1, comparison, size, unsignedp, OPTAB_LIB_WIDEN, |
4364 | &test, &mode); | |
a4da41e1 | 4365 | emit_cmp_and_jump_insn_1 (test, mode, label, prob); |
b30f05db BS |
4366 | } |
4367 | ||
77c9c6c2 RK |
4368 | \f |
4369 | /* Emit a library call comparison between floating point X and Y. | |
4370 | COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.). */ | |
4371 | ||
c5c60e15 | 4372 | static void |
f90b7a5a PB |
4373 | prepare_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison, |
4374 | rtx *ptest, enum machine_mode *pmode) | |
77c9c6c2 | 4375 | { |
c9034561 | 4376 | enum rtx_code swapped = swap_condition (comparison); |
b3f8d95d | 4377 | enum rtx_code reversed = reverse_condition_maybe_unordered (comparison); |
c9034561 | 4378 | enum machine_mode orig_mode = GET_MODE (x); |
7fecf2c7 | 4379 | enum machine_mode mode, cmp_mode; |
6597fd0b | 4380 | rtx true_rtx, false_rtx; |
37bf20ee | 4381 | rtx value, target, insns, equiv; |
0a300065 | 4382 | rtx libfunc = 0; |
b3f8d95d | 4383 | bool reversed_p = false; |
7fecf2c7 | 4384 | cmp_mode = targetm.libgcc_cmp_return_mode (); |
77c9c6c2 | 4385 | |
86556d87 BE |
4386 | for (mode = orig_mode; |
4387 | mode != VOIDmode; | |
4388 | mode = GET_MODE_WIDER_MODE (mode)) | |
77c9c6c2 | 4389 | { |
19b5fafb RH |
4390 | if (code_to_optab (comparison) |
4391 | && (libfunc = optab_libfunc (code_to_optab (comparison), mode))) | |
c9034561 | 4392 | break; |
77c9c6c2 | 4393 | |
19b5fafb RH |
4394 | if (code_to_optab (swapped) |
4395 | && (libfunc = optab_libfunc (code_to_optab (swapped), mode))) | |
77c9c6c2 | 4396 | { |
c9034561 ZW |
4397 | rtx tmp; |
4398 | tmp = x; x = y; y = tmp; | |
4399 | comparison = swapped; | |
4400 | break; | |
77c9c6c2 | 4401 | } |
77c9c6c2 | 4402 | |
19b5fafb RH |
4403 | if (code_to_optab (reversed) |
4404 | && (libfunc = optab_libfunc (code_to_optab (reversed), mode))) | |
b3f8d95d MM |
4405 | { |
4406 | comparison = reversed; | |
4407 | reversed_p = true; | |
4408 | break; | |
4409 | } | |
4410 | } | |
5906d013 | 4411 | |
e3feb571 | 4412 | gcc_assert (mode != VOIDmode); |
0a300065 | 4413 | |
c9034561 ZW |
4414 | if (mode != orig_mode) |
4415 | { | |
4416 | x = convert_to_mode (mode, x, 0); | |
4417 | y = convert_to_mode (mode, y, 0); | |
4418 | } | |
4419 | ||
17796a89 RS |
4420 | /* Attach a REG_EQUAL note describing the semantics of the libcall to |
4421 | the RTL. The allows the RTL optimizers to delete the libcall if the | |
4422 | condition can be determined at compile-time. */ | |
6597fd0b PB |
4423 | if (comparison == UNORDERED |
4424 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) | |
4425 | { | |
4426 | true_rtx = const_true_rtx; | |
4427 | false_rtx = const0_rtx; | |
4428 | } | |
4429 | else | |
4430 | { | |
4431 | switch (comparison) | |
4432 | { | |
4433 | case EQ: | |
4434 | true_rtx = const0_rtx; | |
4435 | false_rtx = const_true_rtx; | |
4436 | break; | |
4437 | ||
4438 | case NE: | |
4439 | true_rtx = const_true_rtx; | |
4440 | false_rtx = const0_rtx; | |
4441 | break; | |
4442 | ||
4443 | case GT: | |
4444 | true_rtx = const1_rtx; | |
4445 | false_rtx = const0_rtx; | |
4446 | break; | |
4447 | ||
4448 | case GE: | |
4449 | true_rtx = const0_rtx; | |
4450 | false_rtx = constm1_rtx; | |
4451 | break; | |
4452 | ||
4453 | case LT: | |
4454 | true_rtx = constm1_rtx; | |
4455 | false_rtx = const0_rtx; | |
4456 | break; | |
4457 | ||
4458 | case LE: | |
4459 | true_rtx = const0_rtx; | |
4460 | false_rtx = const1_rtx; | |
4461 | break; | |
4462 | ||
4463 | default: | |
4464 | gcc_unreachable (); | |
4465 | } | |
4466 | } | |
4467 | ||
17796a89 RS |
4468 | if (comparison == UNORDERED) |
4469 | { | |
7fecf2c7 AP |
4470 | rtx temp = simplify_gen_relational (NE, cmp_mode, mode, x, x); |
4471 | equiv = simplify_gen_relational (NE, cmp_mode, mode, y, y); | |
4472 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, | |
17796a89 RS |
4473 | temp, const_true_rtx, equiv); |
4474 | } | |
4475 | else | |
4476 | { | |
7fecf2c7 | 4477 | equiv = simplify_gen_relational (comparison, cmp_mode, mode, x, y); |
17796a89 | 4478 | if (! FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison)) |
6597fd0b PB |
4479 | equiv = simplify_gen_ternary (IF_THEN_ELSE, cmp_mode, cmp_mode, |
4480 | equiv, true_rtx, false_rtx); | |
bd831d5c | 4481 | } |
37bf20ee RS |
4482 | |
4483 | start_sequence (); | |
4484 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, | |
7fecf2c7 | 4485 | cmp_mode, 2, x, mode, y, mode); |
37bf20ee RS |
4486 | insns = get_insns (); |
4487 | end_sequence (); | |
4488 | ||
7fecf2c7 | 4489 | target = gen_reg_rtx (cmp_mode); |
37bf20ee RS |
4490 | emit_libcall_block (insns, target, value, equiv); |
4491 | ||
c9034561 | 4492 | if (comparison == UNORDERED |
6597fd0b PB |
4493 | || FLOAT_LIB_COMPARE_RETURNS_BOOL (mode, comparison) |
4494 | || reversed_p) | |
4495 | *ptest = gen_rtx_fmt_ee (reversed_p ? EQ : NE, VOIDmode, target, false_rtx); | |
4496 | else | |
4497 | *ptest = gen_rtx_fmt_ee (comparison, VOIDmode, target, const0_rtx); | |
c9034561 | 4498 | |
7fecf2c7 | 4499 | *pmode = cmp_mode; |
77c9c6c2 RK |
4500 | } |
4501 | \f | |
4502 | /* Generate code to indirectly jump to a location given in the rtx LOC. */ | |
4503 | ||
4504 | void | |
0c20a65f | 4505 | emit_indirect_jump (rtx loc) |
77c9c6c2 | 4506 | { |
a5c7d693 | 4507 | struct expand_operand ops[1]; |
77c9c6c2 | 4508 | |
a5c7d693 RS |
4509 | create_address_operand (&ops[0], loc); |
4510 | expand_jump_insn (CODE_FOR_indirect_jump, 1, ops); | |
9649fb4d | 4511 | emit_barrier (); |
77c9c6c2 RK |
4512 | } |
4513 | \f | |
49c4584c DE |
4514 | #ifdef HAVE_conditional_move |
4515 | ||
4516 | /* Emit a conditional move instruction if the machine supports one for that | |
4517 | condition and machine mode. | |
4518 | ||
4519 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4520 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4521 | both be constants. | |
4522 | ||
4523 | OP2 should be stored in TARGET if the comparison is true, otherwise OP3 | |
4524 | should be stored there. MODE is the mode to use should they be constants. | |
4525 | If it is VOIDmode, they cannot both be constants. | |
4526 | ||
4527 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4528 | is not supported. */ | |
4529 | ||
4530 | rtx | |
0c20a65f AJ |
4531 | emit_conditional_move (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4532 | enum machine_mode cmode, rtx op2, rtx op3, | |
4533 | enum machine_mode mode, int unsignedp) | |
49c4584c | 4534 | { |
a5c7d693 | 4535 | rtx tem, comparison, last; |
49c4584c | 4536 | enum insn_code icode; |
e5c56fd9 | 4537 | enum rtx_code reversed; |
49c4584c DE |
4538 | |
4539 | /* If one operand is constant, make it the second one. Only do this | |
4540 | if the other operand is not constant as well. */ | |
4541 | ||
e5c56fd9 | 4542 | if (swap_commutative_operands_p (op0, op1)) |
49c4584c DE |
4543 | { |
4544 | tem = op0; | |
4545 | op0 = op1; | |
4546 | op1 = tem; | |
4547 | code = swap_condition (code); | |
4548 | } | |
4549 | ||
c5c76735 JL |
4550 | /* get_condition will prefer to generate LT and GT even if the old |
4551 | comparison was against zero, so undo that canonicalization here since | |
4552 | comparisons against zero are cheaper. */ | |
87d9741e | 4553 | if (code == LT && op1 == const1_rtx) |
c5c76735 | 4554 | code = LE, op1 = const0_rtx; |
87d9741e | 4555 | else if (code == GT && op1 == constm1_rtx) |
c5c76735 JL |
4556 | code = GE, op1 = const0_rtx; |
4557 | ||
49c4584c DE |
4558 | if (cmode == VOIDmode) |
4559 | cmode = GET_MODE (op0); | |
4560 | ||
e5c56fd9 JH |
4561 | if (swap_commutative_operands_p (op2, op3) |
4562 | && ((reversed = reversed_comparison_code_parts (code, op0, op1, NULL)) | |
4563 | != UNKNOWN)) | |
49c4584c DE |
4564 | { |
4565 | tem = op2; | |
4566 | op2 = op3; | |
4567 | op3 = tem; | |
e5c56fd9 | 4568 | code = reversed; |
49c4584c DE |
4569 | } |
4570 | ||
4571 | if (mode == VOIDmode) | |
4572 | mode = GET_MODE (op2); | |
4573 | ||
f9621cc4 | 4574 | icode = direct_optab_handler (movcc_optab, mode); |
49c4584c DE |
4575 | |
4576 | if (icode == CODE_FOR_nothing) | |
4577 | return 0; | |
4578 | ||
ad76cef8 | 4579 | if (!target) |
49c4584c DE |
4580 | target = gen_reg_rtx (mode); |
4581 | ||
f90b7a5a PB |
4582 | code = unsignedp ? unsigned_condition (code) : code; |
4583 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
49c4584c | 4584 | |
144a5f9d JL |
4585 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4586 | return NULL and let the caller figure out how best to deal with this | |
4587 | situation. */ | |
f90b7a5a | 4588 | if (!COMPARISON_P (comparison)) |
144a5f9d | 4589 | return NULL_RTX; |
0c20a65f | 4590 | |
7f2f0a01 JJ |
4591 | saved_pending_stack_adjust save; |
4592 | save_pending_stack_adjust (&save); | |
a5c7d693 | 4593 | last = get_last_insn (); |
7f2f0a01 | 4594 | do_pending_stack_adjust (); |
f90b7a5a PB |
4595 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), |
4596 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4597 | &comparison, &cmode); | |
a5c7d693 | 4598 | if (comparison) |
f90b7a5a | 4599 | { |
a5c7d693 | 4600 | struct expand_operand ops[4]; |
49c4584c | 4601 | |
a5c7d693 RS |
4602 | create_output_operand (&ops[0], target, mode); |
4603 | create_fixed_operand (&ops[1], comparison); | |
4604 | create_input_operand (&ops[2], op2, mode); | |
4605 | create_input_operand (&ops[3], op3, mode); | |
4606 | if (maybe_expand_insn (icode, 4, ops)) | |
4607 | { | |
4608 | if (ops[0].value != target) | |
4609 | convert_move (target, ops[0].value, false); | |
4610 | return target; | |
4611 | } | |
4612 | } | |
4613 | delete_insns_since (last); | |
7f2f0a01 | 4614 | restore_pending_stack_adjust (&save); |
a5c7d693 | 4615 | return NULL_RTX; |
49c4584c DE |
4616 | } |
4617 | ||
40f03658 | 4618 | /* Return nonzero if a conditional move of mode MODE is supported. |
49c4584c DE |
4619 | |
4620 | This function is for combine so it can tell whether an insn that looks | |
4621 | like a conditional move is actually supported by the hardware. If we | |
4622 | guess wrong we lose a bit on optimization, but that's it. */ | |
4623 | /* ??? sparc64 supports conditionally moving integers values based on fp | |
4624 | comparisons, and vice versa. How do we handle them? */ | |
4625 | ||
4626 | int | |
0c20a65f | 4627 | can_conditionally_move_p (enum machine_mode mode) |
49c4584c | 4628 | { |
f9621cc4 | 4629 | if (direct_optab_handler (movcc_optab, mode) != CODE_FOR_nothing) |
49c4584c DE |
4630 | return 1; |
4631 | ||
4632 | return 0; | |
4633 | } | |
4634 | ||
4635 | #endif /* HAVE_conditional_move */ | |
068f5dea JH |
4636 | |
4637 | /* Emit a conditional addition instruction if the machine supports one for that | |
4638 | condition and machine mode. | |
4639 | ||
4640 | OP0 and OP1 are the operands that should be compared using CODE. CMODE is | |
4641 | the mode to use should they be constants. If it is VOIDmode, they cannot | |
4642 | both be constants. | |
4643 | ||
5285c21c | 4644 | OP2 should be stored in TARGET if the comparison is false, otherwise OP2+OP3 |
068f5dea JH |
4645 | should be stored there. MODE is the mode to use should they be constants. |
4646 | If it is VOIDmode, they cannot both be constants. | |
4647 | ||
4648 | The result is either TARGET (perhaps modified) or NULL_RTX if the operation | |
4649 | is not supported. */ | |
4650 | ||
4651 | rtx | |
0c20a65f AJ |
4652 | emit_conditional_add (rtx target, enum rtx_code code, rtx op0, rtx op1, |
4653 | enum machine_mode cmode, rtx op2, rtx op3, | |
4654 | enum machine_mode mode, int unsignedp) | |
068f5dea | 4655 | { |
a5c7d693 | 4656 | rtx tem, comparison, last; |
068f5dea | 4657 | enum insn_code icode; |
068f5dea JH |
4658 | |
4659 | /* If one operand is constant, make it the second one. Only do this | |
4660 | if the other operand is not constant as well. */ | |
4661 | ||
4662 | if (swap_commutative_operands_p (op0, op1)) | |
4663 | { | |
4664 | tem = op0; | |
4665 | op0 = op1; | |
4666 | op1 = tem; | |
4667 | code = swap_condition (code); | |
4668 | } | |
4669 | ||
4670 | /* get_condition will prefer to generate LT and GT even if the old | |
4671 | comparison was against zero, so undo that canonicalization here since | |
4672 | comparisons against zero are cheaper. */ | |
87d9741e | 4673 | if (code == LT && op1 == const1_rtx) |
068f5dea | 4674 | code = LE, op1 = const0_rtx; |
87d9741e | 4675 | else if (code == GT && op1 == constm1_rtx) |
068f5dea JH |
4676 | code = GE, op1 = const0_rtx; |
4677 | ||
4678 | if (cmode == VOIDmode) | |
4679 | cmode = GET_MODE (op0); | |
4680 | ||
068f5dea JH |
4681 | if (mode == VOIDmode) |
4682 | mode = GET_MODE (op2); | |
4683 | ||
947131ba | 4684 | icode = optab_handler (addcc_optab, mode); |
068f5dea JH |
4685 | |
4686 | if (icode == CODE_FOR_nothing) | |
4687 | return 0; | |
4688 | ||
ad76cef8 | 4689 | if (!target) |
068f5dea JH |
4690 | target = gen_reg_rtx (mode); |
4691 | ||
f90b7a5a PB |
4692 | code = unsignedp ? unsigned_condition (code) : code; |
4693 | comparison = simplify_gen_relational (code, VOIDmode, cmode, op0, op1); | |
068f5dea | 4694 | |
068f5dea JH |
4695 | /* We can get const0_rtx or const_true_rtx in some circumstances. Just |
4696 | return NULL and let the caller figure out how best to deal with this | |
4697 | situation. */ | |
f90b7a5a | 4698 | if (!COMPARISON_P (comparison)) |
068f5dea | 4699 | return NULL_RTX; |
0c20a65f | 4700 | |
f90b7a5a | 4701 | do_pending_stack_adjust (); |
a5c7d693 | 4702 | last = get_last_insn (); |
f90b7a5a PB |
4703 | prepare_cmp_insn (XEXP (comparison, 0), XEXP (comparison, 1), |
4704 | GET_CODE (comparison), NULL_RTX, unsignedp, OPTAB_WIDEN, | |
4705 | &comparison, &cmode); | |
a5c7d693 | 4706 | if (comparison) |
f90b7a5a | 4707 | { |
a5c7d693 | 4708 | struct expand_operand ops[4]; |
068f5dea | 4709 | |
a5c7d693 RS |
4710 | create_output_operand (&ops[0], target, mode); |
4711 | create_fixed_operand (&ops[1], comparison); | |
4712 | create_input_operand (&ops[2], op2, mode); | |
4713 | create_input_operand (&ops[3], op3, mode); | |
4714 | if (maybe_expand_insn (icode, 4, ops)) | |
4715 | { | |
4716 | if (ops[0].value != target) | |
4717 | convert_move (target, ops[0].value, false); | |
4718 | return target; | |
4719 | } | |
4720 | } | |
4721 | delete_insns_since (last); | |
4722 | return NULL_RTX; | |
068f5dea | 4723 | } |
49c4584c | 4724 | \f |
0913e4b4 AO |
4725 | /* These functions attempt to generate an insn body, rather than |
4726 | emitting the insn, but if the gen function already emits them, we | |
ad76cef8 | 4727 | make no attempt to turn them back into naked patterns. */ |
77c9c6c2 RK |
4728 | |
4729 | /* Generate and return an insn body to add Y to X. */ | |
4730 | ||
4731 | rtx | |
0c20a65f | 4732 | gen_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4733 | { |
2ef6ce06 | 4734 | enum insn_code icode = optab_handler (add_optab, GET_MODE (x)); |
77c9c6c2 | 4735 | |
2ef6ce06 RS |
4736 | gcc_assert (insn_operand_matches (icode, 0, x)); |
4737 | gcc_assert (insn_operand_matches (icode, 1, x)); | |
4738 | gcc_assert (insn_operand_matches (icode, 2, y)); | |
77c9c6c2 | 4739 | |
e3feb571 | 4740 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4741 | } |
4742 | ||
e78d8e51 ZW |
4743 | /* Generate and return an insn body to add r1 and c, |
4744 | storing the result in r0. */ | |
8a33f100 | 4745 | |
e78d8e51 | 4746 | rtx |
0c20a65f | 4747 | gen_add3_insn (rtx r0, rtx r1, rtx c) |
e78d8e51 | 4748 | { |
2ef6ce06 | 4749 | enum insn_code icode = optab_handler (add_optab, GET_MODE (r0)); |
e78d8e51 | 4750 | |
7e1a450d | 4751 | if (icode == CODE_FOR_nothing |
2ef6ce06 RS |
4752 | || !insn_operand_matches (icode, 0, r0) |
4753 | || !insn_operand_matches (icode, 1, r1) | |
4754 | || !insn_operand_matches (icode, 2, c)) | |
e78d8e51 ZW |
4755 | return NULL_RTX; |
4756 | ||
e3feb571 | 4757 | return GEN_FCN (icode) (r0, r1, c); |
e78d8e51 ZW |
4758 | } |
4759 | ||
77c9c6c2 | 4760 | int |
0c20a65f | 4761 | have_add2_insn (rtx x, rtx y) |
77c9c6c2 | 4762 | { |
2ef6ce06 | 4763 | enum insn_code icode; |
fb7e77d7 | 4764 | |
e3feb571 | 4765 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4766 | |
2ef6ce06 | 4767 | icode = optab_handler (add_optab, GET_MODE (x)); |
fb7e77d7 TM |
4768 | |
4769 | if (icode == CODE_FOR_nothing) | |
4770 | return 0; | |
4771 | ||
2ef6ce06 RS |
4772 | if (!insn_operand_matches (icode, 0, x) |
4773 | || !insn_operand_matches (icode, 1, x) | |
4774 | || !insn_operand_matches (icode, 2, y)) | |
fb7e77d7 TM |
4775 | return 0; |
4776 | ||
4777 | return 1; | |
77c9c6c2 RK |
4778 | } |
4779 | ||
72a4ddf2 AK |
4780 | /* Generate and return an insn body to add Y to X. */ |
4781 | ||
4782 | rtx | |
4783 | gen_addptr3_insn (rtx x, rtx y, rtx z) | |
4784 | { | |
4785 | enum insn_code icode = optab_handler (addptr3_optab, GET_MODE (x)); | |
4786 | ||
4787 | gcc_assert (insn_operand_matches (icode, 0, x)); | |
4788 | gcc_assert (insn_operand_matches (icode, 1, y)); | |
4789 | gcc_assert (insn_operand_matches (icode, 2, z)); | |
4790 | ||
4791 | return GEN_FCN (icode) (x, y, z); | |
4792 | } | |
4793 | ||
4794 | /* Return true if the target implements an addptr pattern and X, Y, | |
4795 | and Z are valid for the pattern predicates. */ | |
4796 | ||
4797 | int | |
4798 | have_addptr3_insn (rtx x, rtx y, rtx z) | |
4799 | { | |
4800 | enum insn_code icode; | |
4801 | ||
4802 | gcc_assert (GET_MODE (x) != VOIDmode); | |
4803 | ||
4804 | icode = optab_handler (addptr3_optab, GET_MODE (x)); | |
4805 | ||
4806 | if (icode == CODE_FOR_nothing) | |
4807 | return 0; | |
4808 | ||
4809 | if (!insn_operand_matches (icode, 0, x) | |
4810 | || !insn_operand_matches (icode, 1, y) | |
4811 | || !insn_operand_matches (icode, 2, z)) | |
4812 | return 0; | |
4813 | ||
4814 | return 1; | |
4815 | } | |
4816 | ||
77c9c6c2 RK |
4817 | /* Generate and return an insn body to subtract Y from X. */ |
4818 | ||
4819 | rtx | |
0c20a65f | 4820 | gen_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4821 | { |
2ef6ce06 | 4822 | enum insn_code icode = optab_handler (sub_optab, GET_MODE (x)); |
77c9c6c2 | 4823 | |
2ef6ce06 RS |
4824 | gcc_assert (insn_operand_matches (icode, 0, x)); |
4825 | gcc_assert (insn_operand_matches (icode, 1, x)); | |
4826 | gcc_assert (insn_operand_matches (icode, 2, y)); | |
77c9c6c2 | 4827 | |
e3feb571 | 4828 | return GEN_FCN (icode) (x, x, y); |
77c9c6c2 RK |
4829 | } |
4830 | ||
ef89d648 ZW |
4831 | /* Generate and return an insn body to subtract r1 and c, |
4832 | storing the result in r0. */ | |
8a33f100 | 4833 | |
ef89d648 | 4834 | rtx |
0c20a65f | 4835 | gen_sub3_insn (rtx r0, rtx r1, rtx c) |
ef89d648 | 4836 | { |
2ef6ce06 | 4837 | enum insn_code icode = optab_handler (sub_optab, GET_MODE (r0)); |
ef89d648 | 4838 | |
7e1a450d | 4839 | if (icode == CODE_FOR_nothing |
2ef6ce06 RS |
4840 | || !insn_operand_matches (icode, 0, r0) |
4841 | || !insn_operand_matches (icode, 1, r1) | |
4842 | || !insn_operand_matches (icode, 2, c)) | |
ef89d648 ZW |
4843 | return NULL_RTX; |
4844 | ||
e3feb571 | 4845 | return GEN_FCN (icode) (r0, r1, c); |
ef89d648 ZW |
4846 | } |
4847 | ||
77c9c6c2 | 4848 | int |
0c20a65f | 4849 | have_sub2_insn (rtx x, rtx y) |
77c9c6c2 | 4850 | { |
2ef6ce06 | 4851 | enum insn_code icode; |
fb7e77d7 | 4852 | |
e3feb571 | 4853 | gcc_assert (GET_MODE (x) != VOIDmode); |
fb7e77d7 | 4854 | |
2ef6ce06 | 4855 | icode = optab_handler (sub_optab, GET_MODE (x)); |
fb7e77d7 TM |
4856 | |
4857 | if (icode == CODE_FOR_nothing) | |
4858 | return 0; | |
4859 | ||
2ef6ce06 RS |
4860 | if (!insn_operand_matches (icode, 0, x) |
4861 | || !insn_operand_matches (icode, 1, x) | |
4862 | || !insn_operand_matches (icode, 2, y)) | |
fb7e77d7 TM |
4863 | return 0; |
4864 | ||
4865 | return 1; | |
77c9c6c2 RK |
4866 | } |
4867 | ||
e3654226 | 4868 | /* Generate the body of an instruction to copy Y into X. |
2f937369 | 4869 | It may be a list of insns, if one insn isn't enough. */ |
77c9c6c2 RK |
4870 | |
4871 | rtx | |
0c20a65f | 4872 | gen_move_insn (rtx x, rtx y) |
77c9c6c2 | 4873 | { |
e3654226 | 4874 | rtx seq; |
77c9c6c2 | 4875 | |
e3654226 RS |
4876 | start_sequence (); |
4877 | emit_move_insn_1 (x, y); | |
2f937369 | 4878 | seq = get_insns (); |
e3654226 RS |
4879 | end_sequence (); |
4880 | return seq; | |
77c9c6c2 RK |
4881 | } |
4882 | \f | |
34e56753 RS |
4883 | /* Return the insn code used to extend FROM_MODE to TO_MODE. |
4884 | UNSIGNEDP specifies zero-extension instead of sign-extension. If | |
4885 | no such operation exists, CODE_FOR_nothing will be returned. */ | |
77c9c6c2 | 4886 | |
34e56753 | 4887 | enum insn_code |
0c20a65f AJ |
4888 | can_extend_p (enum machine_mode to_mode, enum machine_mode from_mode, |
4889 | int unsignedp) | |
77c9c6c2 | 4890 | { |
85363ca0 | 4891 | convert_optab tab; |
6dd12198 SE |
4892 | #ifdef HAVE_ptr_extend |
4893 | if (unsignedp < 0) | |
4894 | return CODE_FOR_ptr_extend; | |
6dd12198 | 4895 | #endif |
85363ca0 ZW |
4896 | |
4897 | tab = unsignedp ? zext_optab : sext_optab; | |
947131ba | 4898 | return convert_optab_handler (tab, to_mode, from_mode); |
77c9c6c2 RK |
4899 | } |
4900 | ||
4901 | /* Generate the body of an insn to extend Y (with mode MFROM) | |
4902 | into X (with mode MTO). Do zero-extension if UNSIGNEDP is nonzero. */ | |
4903 | ||
4904 | rtx | |
0c20a65f AJ |
4905 | gen_extend_insn (rtx x, rtx y, enum machine_mode mto, |
4906 | enum machine_mode mfrom, int unsignedp) | |
77c9c6c2 | 4907 | { |
85363ca0 ZW |
4908 | enum insn_code icode = can_extend_p (mto, mfrom, unsignedp); |
4909 | return GEN_FCN (icode) (x, y); | |
77c9c6c2 | 4910 | } |
77c9c6c2 RK |
4911 | \f |
4912 | /* can_fix_p and can_float_p say whether the target machine | |
4913 | can directly convert a given fixed point type to | |
4914 | a given floating point type, or vice versa. | |
4915 | The returned value is the CODE_FOR_... value to use, | |
5d81dc5b | 4916 | or CODE_FOR_nothing if these modes cannot be directly converted. |
77c9c6c2 | 4917 | |
5d81dc5b | 4918 | *TRUNCP_PTR is set to 1 if it is necessary to output |
77c9c6c2 RK |
4919 | an explicit FTRUNC insn before the fix insn; otherwise 0. */ |
4920 | ||
4921 | static enum insn_code | |
0c20a65f AJ |
4922 | can_fix_p (enum machine_mode fixmode, enum machine_mode fltmode, |
4923 | int unsignedp, int *truncp_ptr) | |
77c9c6c2 | 4924 | { |
85363ca0 ZW |
4925 | convert_optab tab; |
4926 | enum insn_code icode; | |
4927 | ||
4928 | tab = unsignedp ? ufixtrunc_optab : sfixtrunc_optab; | |
947131ba | 4929 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 ZW |
4930 | if (icode != CODE_FOR_nothing) |
4931 | { | |
4932 | *truncp_ptr = 0; | |
4933 | return icode; | |
4934 | } | |
77c9c6c2 | 4935 | |
0e1d7f32 AH |
4936 | /* FIXME: This requires a port to define both FIX and FTRUNC pattern |
4937 | for this to work. We need to rework the fix* and ftrunc* patterns | |
4938 | and documentation. */ | |
85363ca0 | 4939 | tab = unsignedp ? ufix_optab : sfix_optab; |
947131ba | 4940 | icode = convert_optab_handler (tab, fixmode, fltmode); |
85363ca0 | 4941 | if (icode != CODE_FOR_nothing |
947131ba | 4942 | && optab_handler (ftrunc_optab, fltmode) != CODE_FOR_nothing) |
77c9c6c2 RK |
4943 | { |
4944 | *truncp_ptr = 1; | |
85363ca0 | 4945 | return icode; |
77c9c6c2 | 4946 | } |
85363ca0 ZW |
4947 | |
4948 | *truncp_ptr = 0; | |
77c9c6c2 RK |
4949 | return CODE_FOR_nothing; |
4950 | } | |
4951 | ||
ebeadd91 | 4952 | enum insn_code |
0c20a65f AJ |
4953 | can_float_p (enum machine_mode fltmode, enum machine_mode fixmode, |
4954 | int unsignedp) | |
77c9c6c2 | 4955 | { |
85363ca0 ZW |
4956 | convert_optab tab; |
4957 | ||
4958 | tab = unsignedp ? ufloat_optab : sfloat_optab; | |
947131ba | 4959 | return convert_optab_handler (tab, fltmode, fixmode); |
77c9c6c2 | 4960 | } |
9db8f45d DP |
4961 | |
4962 | /* Function supportable_convert_operation | |
4963 | ||
4964 | Check whether an operation represented by the code CODE is a | |
4965 | convert operation that is supported by the target platform in | |
4966 | vector form (i.e., when operating on arguments of type VECTYPE_IN | |
4967 | producing a result of type VECTYPE_OUT). | |
4968 | ||
4969 | Convert operations we currently support directly are FIX_TRUNC and FLOAT. | |
4970 | This function checks if these operations are supported | |
4971 | by the target platform either directly (via vector tree-codes), or via | |
4972 | target builtins. | |
4973 | ||
4974 | Output: | |
4975 | - CODE1 is code of vector operation to be used when | |
4976 | vectorizing the operation, if available. | |
4977 | - DECL is decl of target builtin functions to be used | |
4978 | when vectorizing the operation, if available. In this case, | |
4979 | CODE1 is CALL_EXPR. */ | |
4980 | ||
4981 | bool | |
4982 | supportable_convert_operation (enum tree_code code, | |
4983 | tree vectype_out, tree vectype_in, | |
4984 | tree *decl, enum tree_code *code1) | |
4985 | { | |
4986 | enum machine_mode m1,m2; | |
4987 | int truncp; | |
4988 | ||
4989 | m1 = TYPE_MODE (vectype_out); | |
4990 | m2 = TYPE_MODE (vectype_in); | |
4991 | ||
4992 | /* First check if we can done conversion directly. */ | |
4993 | if ((code == FIX_TRUNC_EXPR | |
4994 | && can_fix_p (m1,m2,TYPE_UNSIGNED (vectype_out), &truncp) | |
4995 | != CODE_FOR_nothing) | |
4996 | || (code == FLOAT_EXPR | |
4997 | && can_float_p (m1,m2,TYPE_UNSIGNED (vectype_in)) | |
4998 | != CODE_FOR_nothing)) | |
4999 | { | |
5000 | *code1 = code; | |
5001 | return true; | |
5002 | } | |
5003 | ||
5004 | /* Now check for builtin. */ | |
5005 | if (targetm.vectorize.builtin_conversion | |
5006 | && targetm.vectorize.builtin_conversion (code, vectype_out, vectype_in)) | |
5007 | { | |
5008 | *code1 = CALL_EXPR; | |
5009 | *decl = targetm.vectorize.builtin_conversion (code, vectype_out, vectype_in); | |
5010 | return true; | |
5011 | } | |
5012 | return false; | |
5013 | } | |
5014 | ||
77c9c6c2 RK |
5015 | \f |
5016 | /* Generate code to convert FROM to floating point | |
34e56753 | 5017 | and store in TO. FROM must be fixed point and not VOIDmode. |
77c9c6c2 RK |
5018 | UNSIGNEDP nonzero means regard FROM as unsigned. |
5019 | Normally this is done by correcting the final value | |
5020 | if it is negative. */ | |
5021 | ||
5022 | void | |
0c20a65f | 5023 | expand_float (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
5024 | { |
5025 | enum insn_code icode; | |
b3694847 | 5026 | rtx target = to; |
77c9c6c2 | 5027 | enum machine_mode fmode, imode; |
d7735880 | 5028 | bool can_do_signed = false; |
77c9c6c2 | 5029 | |
34e56753 | 5030 | /* Crash now, because we won't be able to decide which mode to use. */ |
e3feb571 | 5031 | gcc_assert (GET_MODE (from) != VOIDmode); |
34e56753 | 5032 | |
77c9c6c2 RK |
5033 | /* Look for an insn to do the conversion. Do it in the specified |
5034 | modes if possible; otherwise convert either input, output or both to | |
5035 | wider mode. If the integer mode is wider than the mode of FROM, | |
5036 | we can do the conversion signed even if the input is unsigned. */ | |
5037 | ||
7bf0a593 AP |
5038 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
5039 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5040 | for (imode = GET_MODE (from); imode != VOIDmode; | |
5041 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
5042 | { |
5043 | int doing_unsigned = unsignedp; | |
5044 | ||
5ba02ca6 | 5045 | if (fmode != GET_MODE (to) |
69660a70 | 5046 | && significand_size (fmode) < GET_MODE_PRECISION (GET_MODE (from))) |
5ba02ca6 GK |
5047 | continue; |
5048 | ||
77c9c6c2 | 5049 | icode = can_float_p (fmode, imode, unsignedp); |
d7735880 JM |
5050 | if (icode == CODE_FOR_nothing && unsignedp) |
5051 | { | |
5052 | enum insn_code scode = can_float_p (fmode, imode, 0); | |
5053 | if (scode != CODE_FOR_nothing) | |
5054 | can_do_signed = true; | |
5055 | if (imode != GET_MODE (from)) | |
5056 | icode = scode, doing_unsigned = 0; | |
5057 | } | |
77c9c6c2 RK |
5058 | |
5059 | if (icode != CODE_FOR_nothing) | |
5060 | { | |
77c9c6c2 RK |
5061 | if (imode != GET_MODE (from)) |
5062 | from = convert_to_mode (imode, from, unsignedp); | |
77c9c6c2 RK |
5063 | |
5064 | if (fmode != GET_MODE (to)) | |
5065 | target = gen_reg_rtx (fmode); | |
5066 | ||
5067 | emit_unop_insn (icode, target, from, | |
5068 | doing_unsigned ? UNSIGNED_FLOAT : FLOAT); | |
5069 | ||
5070 | if (target != to) | |
5071 | convert_move (to, target, 0); | |
5072 | return; | |
5073 | } | |
7e1a450d | 5074 | } |
77c9c6c2 | 5075 | |
6ef9a246 | 5076 | /* Unsigned integer, and no way to convert directly. Convert as signed, |
cc8d36a1 UB |
5077 | then unconditionally adjust the result. */ |
5078 | if (unsignedp && can_do_signed) | |
77c9c6c2 RK |
5079 | { |
5080 | rtx label = gen_label_rtx (); | |
5081 | rtx temp; | |
5082 | REAL_VALUE_TYPE offset; | |
5083 | ||
c95c47f3 PE |
5084 | /* Look for a usable floating mode FMODE wider than the source and at |
5085 | least as wide as the target. Using FMODE will avoid rounding woes | |
5086 | with unsigned values greater than the signed maximum value. */ | |
70864443 | 5087 | |
c95c47f3 PE |
5088 | for (fmode = GET_MODE (to); fmode != VOIDmode; |
5089 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
69660a70 | 5090 | if (GET_MODE_PRECISION (GET_MODE (from)) < GET_MODE_BITSIZE (fmode) |
c95c47f3 PE |
5091 | && can_float_p (fmode, GET_MODE (from), 0) != CODE_FOR_nothing) |
5092 | break; | |
a48fb61b | 5093 | |
c95c47f3 PE |
5094 | if (fmode == VOIDmode) |
5095 | { | |
a48fb61b | 5096 | /* There is no such mode. Pretend the target is wide enough. */ |
c95c47f3 | 5097 | fmode = GET_MODE (to); |
a48fb61b | 5098 | |
0f41302f | 5099 | /* Avoid double-rounding when TO is narrower than FROM. */ |
a48fb61b | 5100 | if ((significand_size (fmode) + 1) |
69660a70 | 5101 | < GET_MODE_PRECISION (GET_MODE (from))) |
a48fb61b RK |
5102 | { |
5103 | rtx temp1; | |
5104 | rtx neglabel = gen_label_rtx (); | |
5105 | ||
0c20a65f | 5106 | /* Don't use TARGET if it isn't a register, is a hard register, |
70864443 | 5107 | or is the wrong mode. */ |
f8cfc6aa | 5108 | if (!REG_P (target) |
70864443 RK |
5109 | || REGNO (target) < FIRST_PSEUDO_REGISTER |
5110 | || GET_MODE (target) != fmode) | |
44f51d4a RK |
5111 | target = gen_reg_rtx (fmode); |
5112 | ||
a48fb61b RK |
5113 | imode = GET_MODE (from); |
5114 | do_pending_stack_adjust (); | |
5115 | ||
5116 | /* Test whether the sign bit is set. */ | |
1c0290ea | 5117 | emit_cmp_and_jump_insns (from, const0_rtx, LT, NULL_RTX, imode, |
a06ef755 | 5118 | 0, neglabel); |
a48fb61b RK |
5119 | |
5120 | /* The sign bit is not set. Convert as signed. */ | |
5121 | expand_float (target, from, 0); | |
5122 | emit_jump_insn (gen_jump (label)); | |
2ad79487 | 5123 | emit_barrier (); |
a48fb61b RK |
5124 | |
5125 | /* The sign bit is set. | |
5126 | Convert to a usable (positive signed) value by shifting right | |
5127 | one bit, while remembering if a nonzero bit was shifted | |
5128 | out; i.e., compute (from & 1) | (from >> 1). */ | |
5129 | ||
5130 | emit_label (neglabel); | |
5131 | temp = expand_binop (imode, and_optab, from, const1_rtx, | |
70864443 | 5132 | NULL_RTX, 1, OPTAB_LIB_WIDEN); |
eb6c3df1 | 5133 | temp1 = expand_shift (RSHIFT_EXPR, imode, from, 1, NULL_RTX, 1); |
0c20a65f | 5134 | temp = expand_binop (imode, ior_optab, temp, temp1, temp, 1, |
70864443 | 5135 | OPTAB_LIB_WIDEN); |
a48fb61b RK |
5136 | expand_float (target, temp, 0); |
5137 | ||
5138 | /* Multiply by 2 to undo the shift above. */ | |
a93738eb | 5139 | temp = expand_binop (fmode, add_optab, target, target, |
7e1a450d | 5140 | target, 0, OPTAB_LIB_WIDEN); |
a93738eb RK |
5141 | if (temp != target) |
5142 | emit_move_insn (target, temp); | |
5143 | ||
a48fb61b RK |
5144 | do_pending_stack_adjust (); |
5145 | emit_label (label); | |
5146 | goto done; | |
5147 | } | |
c95c47f3 PE |
5148 | } |
5149 | ||
77c9c6c2 RK |
5150 | /* If we are about to do some arithmetic to correct for an |
5151 | unsigned operand, do it in a pseudo-register. */ | |
5152 | ||
c95c47f3 | 5153 | if (GET_MODE (to) != fmode |
f8cfc6aa | 5154 | || !REG_P (to) || REGNO (to) < FIRST_PSEUDO_REGISTER) |
c95c47f3 | 5155 | target = gen_reg_rtx (fmode); |
77c9c6c2 RK |
5156 | |
5157 | /* Convert as signed integer to floating. */ | |
5158 | expand_float (target, from, 0); | |
5159 | ||
5160 | /* If FROM is negative (and therefore TO is negative), | |
5161 | correct its value by 2**bitwidth. */ | |
5162 | ||
5163 | do_pending_stack_adjust (); | |
c5d5d461 | 5164 | emit_cmp_and_jump_insns (from, const0_rtx, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5165 | 0, label); |
70864443 | 5166 | |
0c20a65f | 5167 | |
69660a70 | 5168 | real_2expN (&offset, GET_MODE_PRECISION (GET_MODE (from)), fmode); |
c95c47f3 | 5169 | temp = expand_binop (fmode, add_optab, target, |
30d88916 | 5170 | CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode), |
77c9c6c2 RK |
5171 | target, 0, OPTAB_LIB_WIDEN); |
5172 | if (temp != target) | |
5173 | emit_move_insn (target, temp); | |
a48fb61b | 5174 | |
77c9c6c2 RK |
5175 | do_pending_stack_adjust (); |
5176 | emit_label (label); | |
70864443 | 5177 | goto done; |
77c9c6c2 | 5178 | } |
77c9c6c2 | 5179 | |
85363ca0 | 5180 | /* No hardware instruction available; call a library routine. */ |
77c9c6c2 | 5181 | { |
85363ca0 | 5182 | rtx libfunc; |
77c9c6c2 | 5183 | rtx insns; |
9a7f678c | 5184 | rtx value; |
85363ca0 | 5185 | convert_optab tab = unsignedp ? ufloat_optab : sfloat_optab; |
77c9c6c2 | 5186 | |
77c9c6c2 RK |
5187 | if (GET_MODE_SIZE (GET_MODE (from)) < GET_MODE_SIZE (SImode)) |
5188 | from = convert_to_mode (SImode, from, unsignedp); | |
77c9c6c2 | 5189 | |
8a33f100 | 5190 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5191 | gcc_assert (libfunc); |
77c9c6c2 RK |
5192 | |
5193 | start_sequence (); | |
5194 | ||
85363ca0 | 5195 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5196 | GET_MODE (to), 1, from, |
5197 | GET_MODE (from)); | |
77c9c6c2 RK |
5198 | insns = get_insns (); |
5199 | end_sequence (); | |
5200 | ||
9a7f678c | 5201 | emit_libcall_block (insns, target, value, |
d1163987 BW |
5202 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FLOAT : FLOAT, |
5203 | GET_MODE (to), from)); | |
77c9c6c2 RK |
5204 | } |
5205 | ||
a48fb61b RK |
5206 | done: |
5207 | ||
77c9c6c2 RK |
5208 | /* Copy result to requested destination |
5209 | if we have been computing in a temp location. */ | |
5210 | ||
5211 | if (target != to) | |
5212 | { | |
5213 | if (GET_MODE (target) == GET_MODE (to)) | |
5214 | emit_move_insn (to, target); | |
5215 | else | |
5216 | convert_move (to, target, 0); | |
5217 | } | |
5218 | } | |
5219 | \f | |
0e1d7f32 AH |
5220 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5221 | must be floating point. */ | |
77c9c6c2 RK |
5222 | |
5223 | void | |
0c20a65f | 5224 | expand_fix (rtx to, rtx from, int unsignedp) |
77c9c6c2 RK |
5225 | { |
5226 | enum insn_code icode; | |
b3694847 | 5227 | rtx target = to; |
77c9c6c2 RK |
5228 | enum machine_mode fmode, imode; |
5229 | int must_trunc = 0; | |
77c9c6c2 RK |
5230 | |
5231 | /* We first try to find a pair of modes, one real and one integer, at | |
5232 | least as wide as FROM and TO, respectively, in which we can open-code | |
5233 | this conversion. If the integer mode is wider than the mode of TO, | |
5234 | we can do the conversion either signed or unsigned. */ | |
5235 | ||
3987b9db JH |
5236 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5237 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5238 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5239 | imode = GET_MODE_WIDER_MODE (imode)) | |
77c9c6c2 RK |
5240 | { |
5241 | int doing_unsigned = unsignedp; | |
5242 | ||
5243 | icode = can_fix_p (imode, fmode, unsignedp, &must_trunc); | |
5244 | if (icode == CODE_FOR_nothing && imode != GET_MODE (to) && unsignedp) | |
5245 | icode = can_fix_p (imode, fmode, 0, &must_trunc), doing_unsigned = 0; | |
5246 | ||
5247 | if (icode != CODE_FOR_nothing) | |
5248 | { | |
5e04ef8f | 5249 | rtx last = get_last_insn (); |
77c9c6c2 RK |
5250 | if (fmode != GET_MODE (from)) |
5251 | from = convert_to_mode (fmode, from, 0); | |
77c9c6c2 RK |
5252 | |
5253 | if (must_trunc) | |
0e1d7f32 AH |
5254 | { |
5255 | rtx temp = gen_reg_rtx (GET_MODE (from)); | |
5256 | from = expand_unop (GET_MODE (from), ftrunc_optab, from, | |
5257 | temp, 0); | |
5258 | } | |
77c9c6c2 RK |
5259 | |
5260 | if (imode != GET_MODE (to)) | |
5261 | target = gen_reg_rtx (imode); | |
5262 | ||
5e04ef8f JH |
5263 | if (maybe_emit_unop_insn (icode, target, from, |
5264 | doing_unsigned ? UNSIGNED_FIX : FIX)) | |
5265 | { | |
5266 | if (target != to) | |
5267 | convert_move (to, target, unsignedp); | |
5268 | return; | |
5269 | } | |
5270 | delete_insns_since (last); | |
77c9c6c2 RK |
5271 | } |
5272 | } | |
5273 | ||
77c9c6c2 RK |
5274 | /* For an unsigned conversion, there is one more way to do it. |
5275 | If we have a signed conversion, we generate code that compares | |
5276 | the real value to the largest representable positive number. If if | |
5277 | is smaller, the conversion is done normally. Otherwise, subtract | |
5278 | one plus the highest signed number, convert, and add it back. | |
5279 | ||
5280 | We only need to check all real modes, since we know we didn't find | |
0c20a65f | 5281 | anything with a wider integer mode. |
0d446150 JH |
5282 | |
5283 | This code used to extend FP value into mode wider than the destination. | |
6ef9a246 JJ |
5284 | This is needed for decimal float modes which cannot accurately |
5285 | represent one plus the highest signed number of the same size, but | |
5286 | not for binary modes. Consider, for instance conversion from SFmode | |
0d446150 JH |
5287 | into DImode. |
5288 | ||
6fc0bb99 | 5289 | The hot path through the code is dealing with inputs smaller than 2^63 |
0d446150 JH |
5290 | and doing just the conversion, so there is no bits to lose. |
5291 | ||
5292 | In the other path we know the value is positive in the range 2^63..2^64-1 | |
6ef9a246 | 5293 | inclusive. (as for other input overflow happens and result is undefined) |
e0bb17a8 | 5294 | So we know that the most important bit set in mantissa corresponds to |
0d446150 JH |
5295 | 2^63. The subtraction of 2^63 should not generate any rounding as it |
5296 | simply clears out that bit. The rest is trivial. */ | |
77c9c6c2 | 5297 | |
69660a70 | 5298 | if (unsignedp && GET_MODE_PRECISION (GET_MODE (to)) <= HOST_BITS_PER_WIDE_INT) |
77c9c6c2 RK |
5299 | for (fmode = GET_MODE (from); fmode != VOIDmode; |
5300 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
6ef9a246 JJ |
5301 | if (CODE_FOR_nothing != can_fix_p (GET_MODE (to), fmode, 0, &must_trunc) |
5302 | && (!DECIMAL_FLOAT_MODE_P (fmode) | |
69660a70 | 5303 | || GET_MODE_BITSIZE (fmode) > GET_MODE_PRECISION (GET_MODE (to)))) |
77c9c6c2 | 5304 | { |
e9f7ae44 RS |
5305 | int bitsize; |
5306 | REAL_VALUE_TYPE offset; | |
5307 | rtx limit, lab1, lab2, insn; | |
5308 | ||
69660a70 | 5309 | bitsize = GET_MODE_PRECISION (GET_MODE (to)); |
6ef9a246 | 5310 | real_2expN (&offset, bitsize - 1, fmode); |
30d88916 | 5311 | limit = CONST_DOUBLE_FROM_REAL_VALUE (offset, fmode); |
e9f7ae44 RS |
5312 | lab1 = gen_label_rtx (); |
5313 | lab2 = gen_label_rtx (); | |
77c9c6c2 | 5314 | |
77c9c6c2 RK |
5315 | if (fmode != GET_MODE (from)) |
5316 | from = convert_to_mode (fmode, from, 0); | |
5317 | ||
5318 | /* See if we need to do the subtraction. */ | |
5319 | do_pending_stack_adjust (); | |
c5d5d461 | 5320 | emit_cmp_and_jump_insns (from, limit, GE, NULL_RTX, GET_MODE (from), |
a06ef755 | 5321 | 0, lab1); |
77c9c6c2 RK |
5322 | |
5323 | /* If not, do the signed "fix" and branch around fixup code. */ | |
5324 | expand_fix (to, from, 0); | |
5325 | emit_jump_insn (gen_jump (lab2)); | |
5326 | emit_barrier (); | |
5327 | ||
5328 | /* Otherwise, subtract 2**(N-1), convert to signed number, | |
5329 | then add 2**(N-1). Do the addition using XOR since this | |
5330 | will often generate better code. */ | |
5331 | emit_label (lab1); | |
5332 | target = expand_binop (GET_MODE (from), sub_optab, from, limit, | |
b1ec3c92 | 5333 | NULL_RTX, 0, OPTAB_LIB_WIDEN); |
77c9c6c2 RK |
5334 | expand_fix (to, target, 0); |
5335 | target = expand_binop (GET_MODE (to), xor_optab, to, | |
2496c7bd LB |
5336 | gen_int_mode |
5337 | ((HOST_WIDE_INT) 1 << (bitsize - 1), | |
5338 | GET_MODE (to)), | |
77c9c6c2 RK |
5339 | to, 1, OPTAB_LIB_WIDEN); |
5340 | ||
5341 | if (target != to) | |
5342 | emit_move_insn (to, target); | |
5343 | ||
5344 | emit_label (lab2); | |
5345 | ||
947131ba | 5346 | if (optab_handler (mov_optab, GET_MODE (to)) != CODE_FOR_nothing) |
02214a5c RK |
5347 | { |
5348 | /* Make a place for a REG_NOTE and add it. */ | |
5349 | insn = emit_move_insn (to, to); | |
7543f918 JR |
5350 | set_dst_reg_note (insn, REG_EQUAL, |
5351 | gen_rtx_fmt_e (UNSIGNED_FIX, GET_MODE (to), | |
5352 | copy_rtx (from)), | |
5353 | to); | |
02214a5c | 5354 | } |
c5c76735 | 5355 | |
77c9c6c2 RK |
5356 | return; |
5357 | } | |
77c9c6c2 RK |
5358 | |
5359 | /* We can't do it with an insn, so use a library call. But first ensure | |
5360 | that the mode of TO is at least as wide as SImode, since those are the | |
5361 | only library calls we know about. */ | |
5362 | ||
5363 | if (GET_MODE_SIZE (GET_MODE (to)) < GET_MODE_SIZE (SImode)) | |
5364 | { | |
5365 | target = gen_reg_rtx (SImode); | |
5366 | ||
5367 | expand_fix (target, from, unsignedp); | |
5368 | } | |
77c9c6c2 | 5369 | else |
77c9c6c2 RK |
5370 | { |
5371 | rtx insns; | |
560f3f8a | 5372 | rtx value; |
85363ca0 | 5373 | rtx libfunc; |
5906d013 | 5374 | |
85363ca0 | 5375 | convert_optab tab = unsignedp ? ufix_optab : sfix_optab; |
8a33f100 | 5376 | libfunc = convert_optab_libfunc (tab, GET_MODE (to), GET_MODE (from)); |
e3feb571 | 5377 | gcc_assert (libfunc); |
77c9c6c2 | 5378 | |
77c9c6c2 RK |
5379 | start_sequence (); |
5380 | ||
85363ca0 | 5381 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, |
ebb1b59a BS |
5382 | GET_MODE (to), 1, from, |
5383 | GET_MODE (from)); | |
77c9c6c2 RK |
5384 | insns = get_insns (); |
5385 | end_sequence (); | |
5386 | ||
560f3f8a | 5387 | emit_libcall_block (insns, target, value, |
9e6a5703 JC |
5388 | gen_rtx_fmt_e (unsignedp ? UNSIGNED_FIX : FIX, |
5389 | GET_MODE (to), from)); | |
77c9c6c2 | 5390 | } |
0c20a65f | 5391 | |
3e53ea48 RK |
5392 | if (target != to) |
5393 | { | |
5394 | if (GET_MODE (to) == GET_MODE (target)) | |
5395 | emit_move_insn (to, target); | |
5396 | else | |
5397 | convert_move (to, target, 0); | |
5398 | } | |
77c9c6c2 | 5399 | } |
bb7f0423 | 5400 | |
0f996086 CF |
5401 | /* Generate code to convert FROM or TO a fixed-point. |
5402 | If UINTP is true, either TO or FROM is an unsigned integer. | |
5403 | If SATP is true, we need to saturate the result. */ | |
5404 | ||
5405 | void | |
5406 | expand_fixed_convert (rtx to, rtx from, int uintp, int satp) | |
5407 | { | |
5408 | enum machine_mode to_mode = GET_MODE (to); | |
5409 | enum machine_mode from_mode = GET_MODE (from); | |
5410 | convert_optab tab; | |
5411 | enum rtx_code this_code; | |
5412 | enum insn_code code; | |
5413 | rtx insns, value; | |
5414 | rtx libfunc; | |
5415 | ||
5416 | if (to_mode == from_mode) | |
5417 | { | |
5418 | emit_move_insn (to, from); | |
5419 | return; | |
5420 | } | |
5421 | ||
5422 | if (uintp) | |
5423 | { | |
5424 | tab = satp ? satfractuns_optab : fractuns_optab; | |
5425 | this_code = satp ? UNSIGNED_SAT_FRACT : UNSIGNED_FRACT_CONVERT; | |
5426 | } | |
5427 | else | |
5428 | { | |
5429 | tab = satp ? satfract_optab : fract_optab; | |
5430 | this_code = satp ? SAT_FRACT : FRACT_CONVERT; | |
5431 | } | |
947131ba | 5432 | code = convert_optab_handler (tab, to_mode, from_mode); |
0f996086 CF |
5433 | if (code != CODE_FOR_nothing) |
5434 | { | |
5435 | emit_unop_insn (code, to, from, this_code); | |
5436 | return; | |
5437 | } | |
5438 | ||
5439 | libfunc = convert_optab_libfunc (tab, to_mode, from_mode); | |
5440 | gcc_assert (libfunc); | |
5441 | ||
5442 | start_sequence (); | |
5443 | value = emit_library_call_value (libfunc, NULL_RTX, LCT_CONST, to_mode, | |
5444 | 1, from, from_mode); | |
5445 | insns = get_insns (); | |
5446 | end_sequence (); | |
5447 | ||
5448 | emit_libcall_block (insns, to, value, | |
19b5fafb | 5449 | gen_rtx_fmt_e (optab_to_code (tab), to_mode, from)); |
0f996086 CF |
5450 | } |
5451 | ||
bb7f0423 RG |
5452 | /* Generate code to convert FROM to fixed point and store in TO. FROM |
5453 | must be floating point, TO must be signed. Use the conversion optab | |
5454 | TAB to do the conversion. */ | |
5455 | ||
5456 | bool | |
5457 | expand_sfix_optab (rtx to, rtx from, convert_optab tab) | |
5458 | { | |
5459 | enum insn_code icode; | |
5460 | rtx target = to; | |
5461 | enum machine_mode fmode, imode; | |
5462 | ||
5463 | /* We first try to find a pair of modes, one real and one integer, at | |
5464 | least as wide as FROM and TO, respectively, in which we can open-code | |
5465 | this conversion. If the integer mode is wider than the mode of TO, | |
5466 | we can do the conversion either signed or unsigned. */ | |
5467 | ||
5468 | for (fmode = GET_MODE (from); fmode != VOIDmode; | |
5469 | fmode = GET_MODE_WIDER_MODE (fmode)) | |
5470 | for (imode = GET_MODE (to); imode != VOIDmode; | |
5471 | imode = GET_MODE_WIDER_MODE (imode)) | |
5472 | { | |
947131ba | 5473 | icode = convert_optab_handler (tab, imode, fmode); |
bb7f0423 RG |
5474 | if (icode != CODE_FOR_nothing) |
5475 | { | |
5e04ef8f | 5476 | rtx last = get_last_insn (); |
bb7f0423 RG |
5477 | if (fmode != GET_MODE (from)) |
5478 | from = convert_to_mode (fmode, from, 0); | |
5479 | ||
5480 | if (imode != GET_MODE (to)) | |
5481 | target = gen_reg_rtx (imode); | |
5482 | ||
18bd082d | 5483 | if (!maybe_emit_unop_insn (icode, target, from, UNKNOWN)) |
5e04ef8f JH |
5484 | { |
5485 | delete_insns_since (last); | |
5486 | continue; | |
5487 | } | |
bb7f0423 RG |
5488 | if (target != to) |
5489 | convert_move (to, target, 0); | |
5490 | return true; | |
5491 | } | |
5492 | } | |
5493 | ||
5494 | return false; | |
5495 | } | |
77c9c6c2 | 5496 | \f |
ef89d648 ZW |
5497 | /* Report whether we have an instruction to perform the operation |
5498 | specified by CODE on operands of mode MODE. */ | |
5499 | int | |
0c20a65f | 5500 | have_insn_for (enum rtx_code code, enum machine_mode mode) |
ef89d648 | 5501 | { |
19b5fafb RH |
5502 | return (code_to_optab (code) |
5503 | && (optab_handler (code_to_optab (code), mode) | |
ef89d648 ZW |
5504 | != CODE_FOR_nothing)); |
5505 | } | |
5506 | ||
b092b471 JW |
5507 | /* Initialize the libfunc fields of an entire group of entries in some |
5508 | optab. Each entry is set equal to a string consisting of a leading | |
5509 | pair of underscores followed by a generic operation name followed by | |
7ef0daad | 5510 | a mode name (downshifted to lowercase) followed by a single character |
b092b471 JW |
5511 | representing the number of operands for the given operation (which is |
5512 | usually one of the characters '2', '3', or '4'). | |
5513 | ||
5514 | OPTABLE is the table in which libfunc fields are to be initialized. | |
b092b471 JW |
5515 | OPNAME is the generic (string) name of the operation. |
5516 | SUFFIX is the character which specifies the number of operands for | |
5517 | the given generic operation. | |
8a33f100 | 5518 | MODE is the mode to generate for. |
b092b471 JW |
5519 | */ |
5520 | ||
5521 | static void | |
cd1440b1 RH |
5522 | gen_libfunc (optab optable, const char *opname, int suffix, |
5523 | enum machine_mode mode) | |
b092b471 | 5524 | { |
b3694847 | 5525 | unsigned opname_len = strlen (opname); |
8a33f100 JH |
5526 | const char *mname = GET_MODE_NAME (mode); |
5527 | unsigned mname_len = strlen (mname); | |
cdbf4541 BS |
5528 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
5529 | int len = prefix_len + opname_len + mname_len + 1 + 1; | |
5530 | char *libfunc_name = XALLOCAVEC (char, len); | |
8a33f100 JH |
5531 | char *p; |
5532 | const char *q; | |
b092b471 | 5533 | |
8a33f100 JH |
5534 | p = libfunc_name; |
5535 | *p++ = '_'; | |
5536 | *p++ = '_'; | |
cdbf4541 BS |
5537 | if (targetm.libfunc_gnu_prefix) |
5538 | { | |
5539 | *p++ = 'g'; | |
5540 | *p++ = 'n'; | |
5541 | *p++ = 'u'; | |
5542 | *p++ = '_'; | |
5543 | } | |
8a33f100 JH |
5544 | for (q = opname; *q; ) |
5545 | *p++ = *q++; | |
5546 | for (q = mname; *q; q++) | |
5547 | *p++ = TOLOWER (*q); | |
5548 | *p++ = suffix; | |
5549 | *p = '\0'; | |
5550 | ||
5551 | set_optab_libfunc (optable, mode, | |
5552 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
b092b471 JW |
5553 | } |
5554 | ||
8a33f100 | 5555 | /* Like gen_libfunc, but verify that integer operation is involved. */ |
b092b471 | 5556 | |
cd1440b1 | 5557 | void |
8a33f100 JH |
5558 | gen_int_libfunc (optab optable, const char *opname, char suffix, |
5559 | enum machine_mode mode) | |
b092b471 | 5560 | { |
8a33f100 | 5561 | int maxsize = 2 * BITS_PER_WORD; |
2637bd27 | 5562 | int minsize = BITS_PER_WORD; |
8a33f100 JH |
5563 | |
5564 | if (GET_MODE_CLASS (mode) != MODE_INT) | |
5565 | return; | |
c0510d84 DD |
5566 | if (maxsize < LONG_LONG_TYPE_SIZE) |
5567 | maxsize = LONG_LONG_TYPE_SIZE; | |
2637bd27 RB |
5568 | if (minsize > INT_TYPE_SIZE |
5569 | && (trapv_binoptab_p (optable) | |
5570 | || trapv_unoptab_p (optable))) | |
5571 | minsize = INT_TYPE_SIZE; | |
5572 | if (GET_MODE_BITSIZE (mode) < minsize | |
ca0a2d5d | 5573 | || GET_MODE_BITSIZE (mode) > maxsize) |
8a33f100 JH |
5574 | return; |
5575 | gen_libfunc (optable, opname, suffix, mode); | |
b092b471 JW |
5576 | } |
5577 | ||
8a33f100 | 5578 | /* Like gen_libfunc, but verify that FP and set decimal prefix if needed. */ |
b092b471 | 5579 | |
cd1440b1 | 5580 | void |
8a33f100 JH |
5581 | gen_fp_libfunc (optab optable, const char *opname, char suffix, |
5582 | enum machine_mode mode) | |
b092b471 | 5583 | { |
8a33f100 | 5584 | char *dec_opname; |
79b87c74 | 5585 | |
8a33f100 JH |
5586 | if (GET_MODE_CLASS (mode) == MODE_FLOAT) |
5587 | gen_libfunc (optable, opname, suffix, mode); | |
5588 | if (DECIMAL_FLOAT_MODE_P (mode)) | |
5589 | { | |
d3bfe4de | 5590 | dec_opname = XALLOCAVEC (char, sizeof (DECIMAL_PREFIX) + strlen (opname)); |
8a33f100 JH |
5591 | /* For BID support, change the name to have either a bid_ or dpd_ prefix |
5592 | depending on the low level floating format used. */ | |
5593 | memcpy (dec_opname, DECIMAL_PREFIX, sizeof (DECIMAL_PREFIX) - 1); | |
5594 | strcpy (dec_opname + sizeof (DECIMAL_PREFIX) - 1, opname); | |
5595 | gen_libfunc (optable, dec_opname, suffix, mode); | |
5596 | } | |
5597 | } | |
79b87c74 | 5598 | |
0f996086 CF |
5599 | /* Like gen_libfunc, but verify that fixed-point operation is involved. */ |
5600 | ||
cd1440b1 | 5601 | void |
0f996086 CF |
5602 | gen_fixed_libfunc (optab optable, const char *opname, char suffix, |
5603 | enum machine_mode mode) | |
5604 | { | |
5605 | if (!ALL_FIXED_POINT_MODE_P (mode)) | |
5606 | return; | |
5607 | gen_libfunc (optable, opname, suffix, mode); | |
5608 | } | |
5609 | ||
5610 | /* Like gen_libfunc, but verify that signed fixed-point operation is | |
5611 | involved. */ | |
5612 | ||
cd1440b1 | 5613 | void |
0f996086 CF |
5614 | gen_signed_fixed_libfunc (optab optable, const char *opname, char suffix, |
5615 | enum machine_mode mode) | |
5616 | { | |
5617 | if (!SIGNED_FIXED_POINT_MODE_P (mode)) | |
5618 | return; | |
5619 | gen_libfunc (optable, opname, suffix, mode); | |
5620 | } | |
5621 | ||
5622 | /* Like gen_libfunc, but verify that unsigned fixed-point operation is | |
5623 | involved. */ | |
5624 | ||
cd1440b1 | 5625 | void |
0f996086 CF |
5626 | gen_unsigned_fixed_libfunc (optab optable, const char *opname, char suffix, |
5627 | enum machine_mode mode) | |
5628 | { | |
5629 | if (!UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5630 | return; | |
5631 | gen_libfunc (optable, opname, suffix, mode); | |
5632 | } | |
5633 | ||
8a33f100 JH |
5634 | /* Like gen_libfunc, but verify that FP or INT operation is involved. */ |
5635 | ||
cd1440b1 | 5636 | void |
8a33f100 JH |
5637 | gen_int_fp_libfunc (optab optable, const char *name, char suffix, |
5638 | enum machine_mode mode) | |
5639 | { | |
5640 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5641 | gen_fp_libfunc (optable, name, suffix, mode); | |
5642 | if (INTEGRAL_MODE_P (mode)) | |
5643 | gen_int_libfunc (optable, name, suffix, mode); | |
5644 | } | |
5645 | ||
5646 | /* Like gen_libfunc, but verify that FP or INT operation is involved | |
5647 | and add 'v' suffix for integer operation. */ | |
5648 | ||
cd1440b1 | 5649 | void |
8a33f100 JH |
5650 | gen_intv_fp_libfunc (optab optable, const char *name, char suffix, |
5651 | enum machine_mode mode) | |
5652 | { | |
5653 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5654 | gen_fp_libfunc (optable, name, suffix, mode); | |
5655 | if (GET_MODE_CLASS (mode) == MODE_INT) | |
5656 | { | |
5657 | int len = strlen (name); | |
d3bfe4de | 5658 | char *v_name = XALLOCAVEC (char, len + 2); |
8a33f100 JH |
5659 | strcpy (v_name, name); |
5660 | v_name[len] = 'v'; | |
5661 | v_name[len + 1] = 0; | |
5662 | gen_int_libfunc (optable, v_name, suffix, mode); | |
5663 | } | |
b092b471 JW |
5664 | } |
5665 | ||
0f996086 CF |
5666 | /* Like gen_libfunc, but verify that FP or INT or FIXED operation is |
5667 | involved. */ | |
5668 | ||
cd1440b1 | 5669 | void |
0f996086 CF |
5670 | gen_int_fp_fixed_libfunc (optab optable, const char *name, char suffix, |
5671 | enum machine_mode mode) | |
5672 | { | |
5673 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5674 | gen_fp_libfunc (optable, name, suffix, mode); | |
5675 | if (INTEGRAL_MODE_P (mode)) | |
5676 | gen_int_libfunc (optable, name, suffix, mode); | |
5677 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5678 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5679 | } | |
5680 | ||
5681 | /* Like gen_libfunc, but verify that FP or INT or signed FIXED operation is | |
5682 | involved. */ | |
5683 | ||
cd1440b1 | 5684 | void |
0f996086 CF |
5685 | gen_int_fp_signed_fixed_libfunc (optab optable, const char *name, char suffix, |
5686 | enum machine_mode mode) | |
5687 | { | |
5688 | if (DECIMAL_FLOAT_MODE_P (mode) || GET_MODE_CLASS (mode) == MODE_FLOAT) | |
5689 | gen_fp_libfunc (optable, name, suffix, mode); | |
5690 | if (INTEGRAL_MODE_P (mode)) | |
5691 | gen_int_libfunc (optable, name, suffix, mode); | |
5692 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5693 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5694 | } | |
5695 | ||
5696 | /* Like gen_libfunc, but verify that INT or FIXED operation is | |
5697 | involved. */ | |
5698 | ||
cd1440b1 | 5699 | void |
0f996086 CF |
5700 | gen_int_fixed_libfunc (optab optable, const char *name, char suffix, |
5701 | enum machine_mode mode) | |
5702 | { | |
5703 | if (INTEGRAL_MODE_P (mode)) | |
5704 | gen_int_libfunc (optable, name, suffix, mode); | |
5705 | if (ALL_FIXED_POINT_MODE_P (mode)) | |
5706 | gen_fixed_libfunc (optable, name, suffix, mode); | |
5707 | } | |
5708 | ||
5709 | /* Like gen_libfunc, but verify that INT or signed FIXED operation is | |
5710 | involved. */ | |
5711 | ||
cd1440b1 | 5712 | void |
0f996086 CF |
5713 | gen_int_signed_fixed_libfunc (optab optable, const char *name, char suffix, |
5714 | enum machine_mode mode) | |
5715 | { | |
5716 | if (INTEGRAL_MODE_P (mode)) | |
5717 | gen_int_libfunc (optable, name, suffix, mode); | |
5718 | if (SIGNED_FIXED_POINT_MODE_P (mode)) | |
5719 | gen_signed_fixed_libfunc (optable, name, suffix, mode); | |
5720 | } | |
5721 | ||
5722 | /* Like gen_libfunc, but verify that INT or unsigned FIXED operation is | |
5723 | involved. */ | |
5724 | ||
cd1440b1 | 5725 | void |
0f996086 CF |
5726 | gen_int_unsigned_fixed_libfunc (optab optable, const char *name, char suffix, |
5727 | enum machine_mode mode) | |
5728 | { | |
5729 | if (INTEGRAL_MODE_P (mode)) | |
5730 | gen_int_libfunc (optable, name, suffix, mode); | |
5731 | if (UNSIGNED_FIXED_POINT_MODE_P (mode)) | |
5732 | gen_unsigned_fixed_libfunc (optable, name, suffix, mode); | |
5733 | } | |
5734 | ||
85363ca0 ZW |
5735 | /* Initialize the libfunc fields of an entire group of entries of an |
5736 | inter-mode-class conversion optab. The string formation rules are | |
5737 | similar to the ones for init_libfuncs, above, but instead of having | |
5738 | a mode name and an operand count these functions have two mode names | |
5739 | and no operand count. */ | |
8a33f100 | 5740 | |
cd1440b1 | 5741 | void |
8a33f100 JH |
5742 | gen_interclass_conv_libfunc (convert_optab tab, |
5743 | const char *opname, | |
5744 | enum machine_mode tmode, | |
5745 | enum machine_mode fmode) | |
85363ca0 | 5746 | { |
85363ca0 | 5747 | size_t opname_len = strlen (opname); |
8a33f100 | 5748 | size_t mname_len = 0; |
85363ca0 | 5749 | |
85363ca0 ZW |
5750 | const char *fname, *tname; |
5751 | const char *q; | |
cdbf4541 | 5752 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
85363ca0 | 5753 | char *libfunc_name, *suffix; |
79b87c74 | 5754 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5755 | char *p; |
5756 | ||
79b87c74 MM |
5757 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5758 | depends on which underlying decimal floating point format is used. */ | |
5759 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5760 | ||
8a33f100 | 5761 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5762 | |
cdbf4541 | 5763 | nondec_name = XALLOCAVEC (char, prefix_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5764 | nondec_name[0] = '_'; |
5765 | nondec_name[1] = '_'; | |
cdbf4541 BS |
5766 | if (targetm.libfunc_gnu_prefix) |
5767 | { | |
5768 | nondec_name[2] = 'g'; | |
5769 | nondec_name[3] = 'n'; | |
5770 | nondec_name[4] = 'u'; | |
5771 | nondec_name[5] = '_'; | |
5772 | } | |
5773 | ||
5774 | memcpy (&nondec_name[prefix_len], opname, opname_len); | |
5775 | nondec_suffix = nondec_name + opname_len + prefix_len; | |
79b87c74 | 5776 | |
d3bfe4de | 5777 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5778 | dec_name[0] = '_'; |
5779 | dec_name[1] = '_'; | |
5780 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5781 | memcpy (&dec_name[2+dec_len], opname, opname_len); | |
5782 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5783 | |
8a33f100 JH |
5784 | fname = GET_MODE_NAME (fmode); |
5785 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5786 | |
c3284718 | 5787 | if (DECIMAL_FLOAT_MODE_P (fmode) || DECIMAL_FLOAT_MODE_P (tmode)) |
8a33f100 JH |
5788 | { |
5789 | libfunc_name = dec_name; | |
5790 | suffix = dec_suffix; | |
5791 | } | |
5792 | else | |
5793 | { | |
5794 | libfunc_name = nondec_name; | |
5795 | suffix = nondec_suffix; | |
5796 | } | |
79b87c74 | 5797 | |
8a33f100 JH |
5798 | p = suffix; |
5799 | for (q = fname; *q; p++, q++) | |
5800 | *p = TOLOWER (*q); | |
5801 | for (q = tname; *q; p++, q++) | |
5802 | *p = TOLOWER (*q); | |
85363ca0 | 5803 | |
8a33f100 | 5804 | *p = '\0'; |
85363ca0 | 5805 | |
8a33f100 JH |
5806 | set_conv_libfunc (tab, tmode, fmode, |
5807 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5808 | } |
5809 | ||
8a33f100 JH |
5810 | /* Same as gen_interclass_conv_libfunc but verify that we are producing |
5811 | int->fp conversion. */ | |
5812 | ||
cd1440b1 | 5813 | void |
8a33f100 JH |
5814 | gen_int_to_fp_conv_libfunc (convert_optab tab, |
5815 | const char *opname, | |
5816 | enum machine_mode tmode, | |
5817 | enum machine_mode fmode) | |
5818 | { | |
5819 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5820 | return; | |
5821 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5822 | return; | |
5823 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5824 | } | |
5825 | ||
5826 | /* ufloat_optab is special by using floatun for FP and floatuns decimal fp | |
5827 | naming scheme. */ | |
5828 | ||
cd1440b1 | 5829 | void |
8a33f100 JH |
5830 | gen_ufloat_conv_libfunc (convert_optab tab, |
5831 | const char *opname ATTRIBUTE_UNUSED, | |
5832 | enum machine_mode tmode, | |
5833 | enum machine_mode fmode) | |
5834 | { | |
5835 | if (DECIMAL_FLOAT_MODE_P (tmode)) | |
5836 | gen_int_to_fp_conv_libfunc (tab, "floatuns", tmode, fmode); | |
5837 | else | |
5838 | gen_int_to_fp_conv_libfunc (tab, "floatun", tmode, fmode); | |
5839 | } | |
5840 | ||
5841 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5842 | fp->int conversion. */ | |
5843 | ||
cd1440b1 | 5844 | void |
8a33f100 JH |
5845 | gen_int_to_fp_nondecimal_conv_libfunc (convert_optab tab, |
5846 | const char *opname, | |
5847 | enum machine_mode tmode, | |
5848 | enum machine_mode fmode) | |
5849 | { | |
5850 | if (GET_MODE_CLASS (fmode) != MODE_INT) | |
5851 | return; | |
5852 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT) | |
5853 | return; | |
5854 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5855 | } | |
5856 | ||
5857 | /* Same as gen_interclass_conv_libfunc but verify that we are producing | |
5858 | fp->int conversion with no decimal floating point involved. */ | |
5859 | ||
cd1440b1 | 5860 | void |
8a33f100 JH |
5861 | gen_fp_to_int_conv_libfunc (convert_optab tab, |
5862 | const char *opname, | |
5863 | enum machine_mode tmode, | |
5864 | enum machine_mode fmode) | |
5865 | { | |
5866 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5867 | return; | |
5868 | if (GET_MODE_CLASS (tmode) != MODE_INT) | |
5869 | return; | |
5870 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
5871 | } | |
5872 | ||
fa10beec | 5873 | /* Initialize the libfunc fields of an of an intra-mode-class conversion optab. |
8a33f100 JH |
5874 | The string formation rules are |
5875 | similar to the ones for init_libfunc, above. */ | |
5876 | ||
cd1440b1 | 5877 | void |
8a33f100 JH |
5878 | gen_intraclass_conv_libfunc (convert_optab tab, const char *opname, |
5879 | enum machine_mode tmode, enum machine_mode fmode) | |
85363ca0 | 5880 | { |
85363ca0 | 5881 | size_t opname_len = strlen (opname); |
8a33f100 | 5882 | size_t mname_len = 0; |
85363ca0 | 5883 | |
8a33f100 | 5884 | const char *fname, *tname; |
85363ca0 | 5885 | const char *q; |
cdbf4541 | 5886 | int prefix_len = targetm.libfunc_gnu_prefix ? 6 : 2; |
79b87c74 | 5887 | char *nondec_name, *dec_name, *nondec_suffix, *dec_suffix; |
85363ca0 ZW |
5888 | char *libfunc_name, *suffix; |
5889 | char *p; | |
5890 | ||
79b87c74 MM |
5891 | /* If this is a decimal conversion, add the current BID vs. DPD prefix that |
5892 | depends on which underlying decimal floating point format is used. */ | |
5893 | const size_t dec_len = sizeof (DECIMAL_PREFIX) - 1; | |
5894 | ||
8a33f100 | 5895 | mname_len = strlen (GET_MODE_NAME (tmode)) + strlen (GET_MODE_NAME (fmode)); |
85363ca0 | 5896 | |
d3bfe4de | 5897 | nondec_name = XALLOCAVEC (char, 2 + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5898 | nondec_name[0] = '_'; |
5899 | nondec_name[1] = '_'; | |
cdbf4541 BS |
5900 | if (targetm.libfunc_gnu_prefix) |
5901 | { | |
5902 | nondec_name[2] = 'g'; | |
5903 | nondec_name[3] = 'n'; | |
5904 | nondec_name[4] = 'u'; | |
5905 | nondec_name[5] = '_'; | |
5906 | } | |
5907 | memcpy (&nondec_name[prefix_len], opname, opname_len); | |
5908 | nondec_suffix = nondec_name + opname_len + prefix_len; | |
79b87c74 | 5909 | |
d3bfe4de | 5910 | dec_name = XALLOCAVEC (char, 2 + dec_len + opname_len + mname_len + 1 + 1); |
79b87c74 MM |
5911 | dec_name[0] = '_'; |
5912 | dec_name[1] = '_'; | |
5913 | memcpy (&dec_name[2], DECIMAL_PREFIX, dec_len); | |
5914 | memcpy (&dec_name[2 + dec_len], opname, opname_len); | |
5915 | dec_suffix = dec_name + dec_len + opname_len + 2; | |
85363ca0 | 5916 | |
8a33f100 JH |
5917 | fname = GET_MODE_NAME (fmode); |
5918 | tname = GET_MODE_NAME (tmode); | |
85363ca0 | 5919 | |
c3284718 | 5920 | if (DECIMAL_FLOAT_MODE_P (fmode) || DECIMAL_FLOAT_MODE_P (tmode)) |
8a33f100 JH |
5921 | { |
5922 | libfunc_name = dec_name; | |
5923 | suffix = dec_suffix; | |
5924 | } | |
5925 | else | |
5926 | { | |
5927 | libfunc_name = nondec_name; | |
5928 | suffix = nondec_suffix; | |
5929 | } | |
79b87c74 | 5930 | |
8a33f100 JH |
5931 | p = suffix; |
5932 | for (q = fname; *q; p++, q++) | |
5933 | *p = TOLOWER (*q); | |
5934 | for (q = tname; *q; p++, q++) | |
5935 | *p = TOLOWER (*q); | |
85363ca0 | 5936 | |
8a33f100 JH |
5937 | *p++ = '2'; |
5938 | *p = '\0'; | |
85363ca0 | 5939 | |
8a33f100 JH |
5940 | set_conv_libfunc (tab, tmode, fmode, |
5941 | ggc_alloc_string (libfunc_name, p - libfunc_name)); | |
85363ca0 ZW |
5942 | } |
5943 | ||
8a33f100 JH |
5944 | /* Pick proper libcall for trunc_optab. We need to chose if we do |
5945 | truncation or extension and interclass or intraclass. */ | |
5946 | ||
cd1440b1 | 5947 | void |
8a33f100 JH |
5948 | gen_trunc_conv_libfunc (convert_optab tab, |
5949 | const char *opname, | |
5950 | enum machine_mode tmode, | |
5951 | enum machine_mode fmode) | |
5952 | { | |
5953 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5954 | return; | |
5955 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5956 | return; | |
5957 | if (tmode == fmode) | |
5958 | return; | |
5959 | ||
5960 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5961 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5962 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5963 | |
8a33f100 JH |
5964 | if (GET_MODE_PRECISION (fmode) <= GET_MODE_PRECISION (tmode)) |
5965 | return; | |
5966 | ||
5967 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5968 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5969 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5970 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
5971 | } | |
5972 | ||
5973 | /* Pick proper libcall for extend_optab. We need to chose if we do | |
5974 | truncation or extension and interclass or intraclass. */ | |
5975 | ||
cd1440b1 | 5976 | void |
8a33f100 JH |
5977 | gen_extend_conv_libfunc (convert_optab tab, |
5978 | const char *opname ATTRIBUTE_UNUSED, | |
5979 | enum machine_mode tmode, | |
5980 | enum machine_mode fmode) | |
5981 | { | |
5982 | if (GET_MODE_CLASS (tmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (tmode)) | |
5983 | return; | |
5984 | if (GET_MODE_CLASS (fmode) != MODE_FLOAT && !DECIMAL_FLOAT_MODE_P (fmode)) | |
5985 | return; | |
5986 | if (tmode == fmode) | |
5987 | return; | |
5988 | ||
5989 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (fmode)) | |
5990 | || (GET_MODE_CLASS (fmode) == MODE_FLOAT && DECIMAL_FLOAT_MODE_P (tmode))) | |
5991 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
b8698a0f | 5992 | |
8a33f100 JH |
5993 | if (GET_MODE_PRECISION (fmode) > GET_MODE_PRECISION (tmode)) |
5994 | return; | |
5995 | ||
5996 | if ((GET_MODE_CLASS (tmode) == MODE_FLOAT | |
5997 | && GET_MODE_CLASS (fmode) == MODE_FLOAT) | |
5998 | || (DECIMAL_FLOAT_MODE_P (fmode) && DECIMAL_FLOAT_MODE_P (tmode))) | |
5999 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
6000 | } | |
85363ca0 | 6001 | |
0f996086 CF |
6002 | /* Pick proper libcall for fract_optab. We need to chose if we do |
6003 | interclass or intraclass. */ | |
6004 | ||
cd1440b1 | 6005 | void |
0f996086 CF |
6006 | gen_fract_conv_libfunc (convert_optab tab, |
6007 | const char *opname, | |
6008 | enum machine_mode tmode, | |
6009 | enum machine_mode fmode) | |
6010 | { | |
6011 | if (tmode == fmode) | |
6012 | return; | |
6013 | if (!(ALL_FIXED_POINT_MODE_P (tmode) || ALL_FIXED_POINT_MODE_P (fmode))) | |
6014 | return; | |
6015 | ||
6016 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
6017 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
6018 | else | |
6019 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
6020 | } | |
6021 | ||
6022 | /* Pick proper libcall for fractuns_optab. */ | |
6023 | ||
cd1440b1 | 6024 | void |
0f996086 CF |
6025 | gen_fractuns_conv_libfunc (convert_optab tab, |
6026 | const char *opname, | |
6027 | enum machine_mode tmode, | |
6028 | enum machine_mode fmode) | |
6029 | { | |
6030 | if (tmode == fmode) | |
6031 | return; | |
6032 | /* One mode must be a fixed-point mode, and the other must be an integer | |
6033 | mode. */ | |
6034 | if (!((ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT) | |
6035 | || (ALL_FIXED_POINT_MODE_P (fmode) | |
6036 | && GET_MODE_CLASS (tmode) == MODE_INT))) | |
6037 | return; | |
6038 | ||
6039 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
6040 | } | |
6041 | ||
6042 | /* Pick proper libcall for satfract_optab. We need to chose if we do | |
6043 | interclass or intraclass. */ | |
6044 | ||
cd1440b1 | 6045 | void |
0f996086 CF |
6046 | gen_satfract_conv_libfunc (convert_optab tab, |
6047 | const char *opname, | |
6048 | enum machine_mode tmode, | |
6049 | enum machine_mode fmode) | |
6050 | { | |
6051 | if (tmode == fmode) | |
6052 | return; | |
6053 | /* TMODE must be a fixed-point mode. */ | |
6054 | if (!ALL_FIXED_POINT_MODE_P (tmode)) | |
6055 | return; | |
6056 | ||
6057 | if (GET_MODE_CLASS (tmode) == GET_MODE_CLASS (fmode)) | |
6058 | gen_intraclass_conv_libfunc (tab, opname, tmode, fmode); | |
6059 | else | |
6060 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
6061 | } | |
6062 | ||
6063 | /* Pick proper libcall for satfractuns_optab. */ | |
6064 | ||
cd1440b1 | 6065 | void |
0f996086 CF |
6066 | gen_satfractuns_conv_libfunc (convert_optab tab, |
6067 | const char *opname, | |
6068 | enum machine_mode tmode, | |
6069 | enum machine_mode fmode) | |
6070 | { | |
6071 | if (tmode == fmode) | |
6072 | return; | |
6073 | /* TMODE must be a fixed-point mode, and FMODE must be an integer mode. */ | |
6074 | if (!(ALL_FIXED_POINT_MODE_P (tmode) && GET_MODE_CLASS (fmode) == MODE_INT)) | |
6075 | return; | |
6076 | ||
6077 | gen_interclass_conv_libfunc (tab, opname, tmode, fmode); | |
6078 | } | |
6079 | ||
61698f54 RS |
6080 | /* A table of previously-created libfuncs, hashed by name. */ |
6081 | static GTY ((param_is (union tree_node))) htab_t libfunc_decls; | |
52859c77 | 6082 | |
61698f54 | 6083 | /* Hashtable callbacks for libfunc_decls. */ |
ee1315aa | 6084 | |
61698f54 RS |
6085 | static hashval_t |
6086 | libfunc_decl_hash (const void *entry) | |
6087 | { | |
6456e26e | 6088 | return IDENTIFIER_HASH_VALUE (DECL_NAME ((const_tree) entry)); |
61698f54 | 6089 | } |
52859c77 | 6090 | |
61698f54 RS |
6091 | static int |
6092 | libfunc_decl_eq (const void *entry1, const void *entry2) | |
6093 | { | |
572e5ae3 | 6094 | return DECL_NAME ((const_tree) entry1) == (const_tree) entry2; |
61698f54 | 6095 | } |
52859c77 | 6096 | |
f9417da1 RG |
6097 | /* Build a decl for a libfunc named NAME. */ |
6098 | ||
6099 | tree | |
6100 | build_libfunc_function (const char *name) | |
6101 | { | |
6102 | tree decl = build_decl (UNKNOWN_LOCATION, FUNCTION_DECL, | |
6103 | get_identifier (name), | |
6104 | build_function_type (integer_type_node, NULL_TREE)); | |
6105 | /* ??? We don't have any type information except for this is | |
6106 | a function. Pretend this is "int foo()". */ | |
6107 | DECL_ARTIFICIAL (decl) = 1; | |
6108 | DECL_EXTERNAL (decl) = 1; | |
6109 | TREE_PUBLIC (decl) = 1; | |
6110 | gcc_assert (DECL_ASSEMBLER_NAME (decl)); | |
6111 | ||
6112 | /* Zap the nonsensical SYMBOL_REF_DECL for this. What we're left with | |
6113 | are the flags assigned by targetm.encode_section_info. */ | |
6114 | SET_SYMBOL_REF_DECL (XEXP (DECL_RTL (decl), 0), NULL); | |
6115 | ||
6116 | return decl; | |
6117 | } | |
6118 | ||
61698f54 RS |
6119 | rtx |
6120 | init_one_libfunc (const char *name) | |
6121 | { | |
6122 | tree id, decl; | |
6123 | void **slot; | |
6124 | hashval_t hash; | |
6125 | ||
6126 | if (libfunc_decls == NULL) | |
6127 | libfunc_decls = htab_create_ggc (37, libfunc_decl_hash, | |
6128 | libfunc_decl_eq, NULL); | |
6129 | ||
6130 | /* See if we have already created a libfunc decl for this function. */ | |
6131 | id = get_identifier (name); | |
eef4a603 | 6132 | hash = IDENTIFIER_HASH_VALUE (id); |
61698f54 RS |
6133 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, INSERT); |
6134 | decl = (tree) *slot; | |
6135 | if (decl == NULL) | |
6136 | { | |
6137 | /* Create a new decl, so that it can be passed to | |
6138 | targetm.encode_section_info. */ | |
f9417da1 | 6139 | decl = build_libfunc_function (name); |
61698f54 RS |
6140 | *slot = decl; |
6141 | } | |
6142 | return XEXP (DECL_RTL (decl), 0); | |
76095e2f RH |
6143 | } |
6144 | ||
6b2b8871 JJ |
6145 | /* Adjust the assembler name of libfunc NAME to ASMSPEC. */ |
6146 | ||
6147 | rtx | |
6148 | set_user_assembler_libfunc (const char *name, const char *asmspec) | |
6149 | { | |
6150 | tree id, decl; | |
6151 | void **slot; | |
6152 | hashval_t hash; | |
6153 | ||
6154 | id = get_identifier (name); | |
eef4a603 | 6155 | hash = IDENTIFIER_HASH_VALUE (id); |
6b2b8871 JJ |
6156 | slot = htab_find_slot_with_hash (libfunc_decls, id, hash, NO_INSERT); |
6157 | gcc_assert (slot); | |
6158 | decl = (tree) *slot; | |
6159 | set_user_assembler_name (decl, asmspec); | |
6160 | return XEXP (DECL_RTL (decl), 0); | |
6161 | } | |
6162 | ||
c15c90bb ZW |
6163 | /* Call this to reset the function entry for one optab (OPTABLE) in mode |
6164 | MODE to NAME, which should be either 0 or a string constant. */ | |
6165 | void | |
cd1440b1 | 6166 | set_optab_libfunc (optab op, enum machine_mode mode, const char *name) |
c15c90bb | 6167 | { |
8a33f100 JH |
6168 | rtx val; |
6169 | struct libfunc_entry e; | |
6170 | struct libfunc_entry **slot; | |
cd1440b1 RH |
6171 | |
6172 | e.op = op; | |
8a33f100 JH |
6173 | e.mode1 = mode; |
6174 | e.mode2 = VOIDmode; | |
6175 | ||
c15c90bb | 6176 | if (name) |
8a33f100 | 6177 | val = init_one_libfunc (name); |
c15c90bb | 6178 | else |
8a33f100 JH |
6179 | val = 0; |
6180 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6181 | if (*slot == NULL) | |
766090c2 | 6182 | *slot = ggc_alloc<libfunc_entry> (); |
cd1440b1 | 6183 | (*slot)->op = op; |
8a33f100 JH |
6184 | (*slot)->mode1 = mode; |
6185 | (*slot)->mode2 = VOIDmode; | |
6186 | (*slot)->libfunc = val; | |
c15c90bb ZW |
6187 | } |
6188 | ||
85363ca0 ZW |
6189 | /* Call this to reset the function entry for one conversion optab |
6190 | (OPTABLE) from mode FMODE to mode TMODE to NAME, which should be | |
6191 | either 0 or a string constant. */ | |
6192 | void | |
cd1440b1 | 6193 | set_conv_libfunc (convert_optab optab, enum machine_mode tmode, |
85363ca0 ZW |
6194 | enum machine_mode fmode, const char *name) |
6195 | { | |
8a33f100 JH |
6196 | rtx val; |
6197 | struct libfunc_entry e; | |
6198 | struct libfunc_entry **slot; | |
cd1440b1 RH |
6199 | |
6200 | e.op = optab; | |
8a33f100 JH |
6201 | e.mode1 = tmode; |
6202 | e.mode2 = fmode; | |
6203 | ||
85363ca0 | 6204 | if (name) |
8a33f100 | 6205 | val = init_one_libfunc (name); |
85363ca0 | 6206 | else |
8a33f100 JH |
6207 | val = 0; |
6208 | slot = (struct libfunc_entry **) htab_find_slot (libfunc_hash, &e, INSERT); | |
6209 | if (*slot == NULL) | |
766090c2 | 6210 | *slot = ggc_alloc<libfunc_entry> (); |
cd1440b1 | 6211 | (*slot)->op = optab; |
8a33f100 JH |
6212 | (*slot)->mode1 = tmode; |
6213 | (*slot)->mode2 = fmode; | |
6214 | (*slot)->libfunc = val; | |
85363ca0 ZW |
6215 | } |
6216 | ||
b5deb7b6 | 6217 | /* Call this to initialize the contents of the optabs |
77c9c6c2 RK |
6218 | appropriately for the current target machine. */ |
6219 | ||
6220 | void | |
0c20a65f | 6221 | init_optabs (void) |
77c9c6c2 | 6222 | { |
3e9c326a | 6223 | if (libfunc_hash) |
cd1440b1 | 6224 | htab_empty (libfunc_hash); |
3e9c326a RS |
6225 | else |
6226 | libfunc_hash = htab_create_ggc (10, hash_libfunc, eq_libfunc, NULL); | |
c0742514 | 6227 | |
5d81dc5b | 6228 | /* Fill in the optabs with the insns we support. */ |
135204dd | 6229 | init_all_optabs (this_fn_optabs); |
5d81dc5b | 6230 | |
8a33f100 JH |
6231 | /* The ffs function operates on `int'. Fall back on it if we do not |
6232 | have a libgcc2 function for that width. */ | |
6233 | if (INT_TYPE_SIZE < BITS_PER_WORD) | |
0f900dfa JJ |
6234 | set_optab_libfunc (ffs_optab, mode_for_size (INT_TYPE_SIZE, MODE_INT, 0), |
6235 | "ffs"); | |
76095e2f | 6236 | |
167fa32c EC |
6237 | /* Explicitly initialize the bswap libfuncs since we need them to be |
6238 | valid for things other than word_mode. */ | |
cdbf4541 BS |
6239 | if (targetm.libfunc_gnu_prefix) |
6240 | { | |
6241 | set_optab_libfunc (bswap_optab, SImode, "__gnu_bswapsi2"); | |
6242 | set_optab_libfunc (bswap_optab, DImode, "__gnu_bswapdi2"); | |
6243 | } | |
6244 | else | |
6245 | { | |
6246 | set_optab_libfunc (bswap_optab, SImode, "__bswapsi2"); | |
6247 | set_optab_libfunc (bswap_optab, DImode, "__bswapdi2"); | |
6248 | } | |
167fa32c | 6249 | |
85363ca0 ZW |
6250 | /* Use cabs for double complex abs, since systems generally have cabs. |
6251 | Don't define any libcall for float complex, so that cabs will be used. */ | |
6252 | if (complex_double_type_node) | |
cd1440b1 RH |
6253 | set_optab_libfunc (abs_optab, TYPE_MODE (complex_double_type_node), |
6254 | "cabs"); | |
76095e2f | 6255 | |
9602f5a0 | 6256 | abort_libfunc = init_one_libfunc ("abort"); |
76095e2f | 6257 | memcpy_libfunc = init_one_libfunc ("memcpy"); |
b215b52e | 6258 | memmove_libfunc = init_one_libfunc ("memmove"); |
76095e2f | 6259 | memcmp_libfunc = init_one_libfunc ("memcmp"); |
76095e2f | 6260 | memset_libfunc = init_one_libfunc ("memset"); |
68d28100 | 6261 | setbits_libfunc = init_one_libfunc ("__setbits"); |
76095e2f | 6262 | |
6e6a07d2 | 6263 | #ifndef DONT_USE_BUILTIN_SETJMP |
76095e2f RH |
6264 | setjmp_libfunc = init_one_libfunc ("__builtin_setjmp"); |
6265 | longjmp_libfunc = init_one_libfunc ("__builtin_longjmp"); | |
27a36778 | 6266 | #else |
76095e2f RH |
6267 | setjmp_libfunc = init_one_libfunc ("setjmp"); |
6268 | longjmp_libfunc = init_one_libfunc ("longjmp"); | |
27a36778 | 6269 | #endif |
52a11cbf RH |
6270 | unwind_sjlj_register_libfunc = init_one_libfunc ("_Unwind_SjLj_Register"); |
6271 | unwind_sjlj_unregister_libfunc | |
6272 | = init_one_libfunc ("_Unwind_SjLj_Unregister"); | |
6adb4e3a | 6273 | |
07417085 KR |
6274 | /* For function entry/exit instrumentation. */ |
6275 | profile_function_entry_libfunc | |
76095e2f | 6276 | = init_one_libfunc ("__cyg_profile_func_enter"); |
07417085 | 6277 | profile_function_exit_libfunc |
76095e2f | 6278 | = init_one_libfunc ("__cyg_profile_func_exit"); |
07417085 | 6279 | |
68d28100 | 6280 | gcov_flush_libfunc = init_one_libfunc ("__gcov_flush"); |
68d28100 | 6281 | |
159c2aed | 6282 | /* Allow the target to add more libcalls or rename some, etc. */ |
c15c90bb | 6283 | targetm.init_libfuncs (); |
77c9c6c2 | 6284 | } |
b3f8d95d | 6285 | |
4b1baac8 RS |
6286 | /* Use the current target and options to initialize |
6287 | TREE_OPTIMIZATION_OPTABS (OPTNODE). */ | |
135204dd AH |
6288 | |
6289 | void | |
4b1baac8 | 6290 | init_tree_optimization_optabs (tree optnode) |
135204dd | 6291 | { |
4b1baac8 RS |
6292 | /* Quick exit if we have already computed optabs for this target. */ |
6293 | if (TREE_OPTIMIZATION_BASE_OPTABS (optnode) == this_target_optabs) | |
6294 | return; | |
135204dd | 6295 | |
4b1baac8 RS |
6296 | /* Forget any previous information and set up for the current target. */ |
6297 | TREE_OPTIMIZATION_BASE_OPTABS (optnode) = this_target_optabs; | |
135204dd | 6298 | struct target_optabs *tmp_optabs = (struct target_optabs *) |
4b1baac8 RS |
6299 | TREE_OPTIMIZATION_OPTABS (optnode); |
6300 | if (tmp_optabs) | |
6301 | memset (tmp_optabs, 0, sizeof (struct target_optabs)); | |
6302 | else | |
766090c2 | 6303 | tmp_optabs = ggc_alloc<target_optabs> (); |
135204dd AH |
6304 | |
6305 | /* Generate a new set of optabs into tmp_optabs. */ | |
6306 | init_all_optabs (tmp_optabs); | |
6307 | ||
6308 | /* If the optabs changed, record it. */ | |
6309 | if (memcmp (tmp_optabs, this_target_optabs, sizeof (struct target_optabs))) | |
cc349a39 | 6310 | TREE_OPTIMIZATION_OPTABS (optnode) = tmp_optabs; |
135204dd AH |
6311 | else |
6312 | { | |
6313 | TREE_OPTIMIZATION_OPTABS (optnode) = NULL; | |
6314 | ggc_free (tmp_optabs); | |
6315 | } | |
6316 | } | |
6317 | ||
cedb4a1a RH |
6318 | /* A helper function for init_sync_libfuncs. Using the basename BASE, |
6319 | install libfuncs into TAB for BASE_N for 1 <= N <= MAX. */ | |
6320 | ||
6321 | static void | |
6322 | init_sync_libfuncs_1 (optab tab, const char *base, int max) | |
6323 | { | |
6324 | enum machine_mode mode; | |
6325 | char buf[64]; | |
6326 | size_t len = strlen (base); | |
6327 | int i; | |
6328 | ||
6329 | gcc_assert (max <= 8); | |
6330 | gcc_assert (len + 3 < sizeof (buf)); | |
6331 | ||
6332 | memcpy (buf, base, len); | |
6333 | buf[len] = '_'; | |
6334 | buf[len + 1] = '0'; | |
6335 | buf[len + 2] = '\0'; | |
6336 | ||
6337 | mode = QImode; | |
022c0cd1 | 6338 | for (i = 1; i <= max; i *= 2) |
cedb4a1a RH |
6339 | { |
6340 | buf[len + 1] = '0' + i; | |
6341 | set_optab_libfunc (tab, mode, buf); | |
6342 | mode = GET_MODE_2XWIDER_MODE (mode); | |
6343 | } | |
6344 | } | |
6345 | ||
6346 | void | |
6347 | init_sync_libfuncs (int max) | |
6348 | { | |
e8053cf5 RH |
6349 | if (!flag_sync_libcalls) |
6350 | return; | |
6351 | ||
cedb4a1a RH |
6352 | init_sync_libfuncs_1 (sync_compare_and_swap_optab, |
6353 | "__sync_val_compare_and_swap", max); | |
6354 | init_sync_libfuncs_1 (sync_lock_test_and_set_optab, | |
6355 | "__sync_lock_test_and_set", max); | |
6356 | ||
6357 | init_sync_libfuncs_1 (sync_old_add_optab, "__sync_fetch_and_add", max); | |
6358 | init_sync_libfuncs_1 (sync_old_sub_optab, "__sync_fetch_and_sub", max); | |
ff47a151 | 6359 | init_sync_libfuncs_1 (sync_old_ior_optab, "__sync_fetch_and_or", max); |
cedb4a1a RH |
6360 | init_sync_libfuncs_1 (sync_old_and_optab, "__sync_fetch_and_and", max); |
6361 | init_sync_libfuncs_1 (sync_old_xor_optab, "__sync_fetch_and_xor", max); | |
6362 | init_sync_libfuncs_1 (sync_old_nand_optab, "__sync_fetch_and_nand", max); | |
6363 | ||
6364 | init_sync_libfuncs_1 (sync_new_add_optab, "__sync_add_and_fetch", max); | |
6365 | init_sync_libfuncs_1 (sync_new_sub_optab, "__sync_sub_and_fetch", max); | |
ff47a151 | 6366 | init_sync_libfuncs_1 (sync_new_ior_optab, "__sync_or_and_fetch", max); |
cedb4a1a RH |
6367 | init_sync_libfuncs_1 (sync_new_and_optab, "__sync_and_and_fetch", max); |
6368 | init_sync_libfuncs_1 (sync_new_xor_optab, "__sync_xor_and_fetch", max); | |
6369 | init_sync_libfuncs_1 (sync_new_nand_optab, "__sync_nand_and_fetch", max); | |
6370 | } | |
6371 | ||
b3f8d95d MM |
6372 | /* Print information about the current contents of the optabs on |
6373 | STDERR. */ | |
6374 | ||
24e47c76 | 6375 | DEBUG_FUNCTION void |
b3f8d95d MM |
6376 | debug_optab_libfuncs (void) |
6377 | { | |
cd1440b1 | 6378 | int i, j, k; |
b3f8d95d MM |
6379 | |
6380 | /* Dump the arithmetic optabs. */ | |
cd1440b1 | 6381 | for (i = FIRST_NORM_OPTAB; i <= LAST_NORMLIB_OPTAB; ++i) |
b3f8d95d MM |
6382 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6383 | { | |
cd1440b1 | 6384 | rtx l = optab_libfunc ((optab) i, (enum machine_mode) j); |
8a33f100 | 6385 | if (l) |
b3f8d95d | 6386 | { |
8a33f100 | 6387 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6388 | fprintf (stderr, "%s\t%s:\t%s\n", |
cd1440b1 | 6389 | GET_RTX_NAME (optab_to_code ((optab) i)), |
b3f8d95d | 6390 | GET_MODE_NAME (j), |
8a33f100 | 6391 | XSTR (l, 0)); |
b3f8d95d MM |
6392 | } |
6393 | } | |
6394 | ||
6395 | /* Dump the conversion optabs. */ | |
cd1440b1 | 6396 | for (i = FIRST_CONV_OPTAB; i <= LAST_CONVLIB_OPTAB; ++i) |
b3f8d95d MM |
6397 | for (j = 0; j < NUM_MACHINE_MODES; ++j) |
6398 | for (k = 0; k < NUM_MACHINE_MODES; ++k) | |
6399 | { | |
cd1440b1 RH |
6400 | rtx l = convert_optab_libfunc ((optab) i, (enum machine_mode) j, |
6401 | (enum machine_mode) k); | |
8a33f100 | 6402 | if (l) |
b3f8d95d | 6403 | { |
8a33f100 | 6404 | gcc_assert (GET_CODE (l) == SYMBOL_REF); |
5906d013 | 6405 | fprintf (stderr, "%s\t%s\t%s:\t%s\n", |
cd1440b1 | 6406 | GET_RTX_NAME (optab_to_code ((optab) i)), |
b3f8d95d MM |
6407 | GET_MODE_NAME (j), |
6408 | GET_MODE_NAME (k), | |
8a33f100 | 6409 | XSTR (l, 0)); |
b3f8d95d MM |
6410 | } |
6411 | } | |
6412 | } | |
6413 | ||
7e1966ca | 6414 | \f |
e0cd0770 JC |
6415 | /* Generate insns to trap with code TCODE if OP1 and OP2 satisfy condition |
6416 | CODE. Return 0 on failure. */ | |
6417 | ||
6418 | rtx | |
f90b7a5a | 6419 | gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) |
e0cd0770 JC |
6420 | { |
6421 | enum machine_mode mode = GET_MODE (op1); | |
842a431a DM |
6422 | enum insn_code icode; |
6423 | rtx insn; | |
f90b7a5a | 6424 | rtx trap_rtx; |
e0cd0770 JC |
6425 | |
6426 | if (mode == VOIDmode) | |
6427 | return 0; | |
6428 | ||
947131ba | 6429 | icode = optab_handler (ctrap_optab, mode); |
842a431a DM |
6430 | if (icode == CODE_FOR_nothing) |
6431 | return 0; | |
6432 | ||
f90b7a5a | 6433 | /* Some targets only accept a zero trap code. */ |
2ef6ce06 | 6434 | if (!insn_operand_matches (icode, 3, tcode)) |
f90b7a5a PB |
6435 | return 0; |
6436 | ||
6437 | do_pending_stack_adjust (); | |
842a431a | 6438 | start_sequence (); |
f90b7a5a PB |
6439 | prepare_cmp_insn (op1, op2, code, NULL_RTX, false, OPTAB_DIRECT, |
6440 | &trap_rtx, &mode); | |
6441 | if (!trap_rtx) | |
6442 | insn = NULL_RTX; | |
6443 | else | |
6444 | insn = GEN_FCN (icode) (trap_rtx, XEXP (trap_rtx, 0), XEXP (trap_rtx, 1), | |
6445 | tcode); | |
6446 | ||
6447 | /* If that failed, then give up. */ | |
6448 | if (insn == 0) | |
d893ccde RH |
6449 | { |
6450 | end_sequence (); | |
6451 | return 0; | |
6452 | } | |
842a431a | 6453 | |
f90b7a5a PB |
6454 | emit_insn (insn); |
6455 | insn = get_insns (); | |
842a431a | 6456 | end_sequence (); |
842a431a | 6457 | return insn; |
e0cd0770 | 6458 | } |
e2500fed | 6459 | |
7ce67fbe DP |
6460 | /* Return rtx code for TCODE. Use UNSIGNEDP to select signed |
6461 | or unsigned operation code. */ | |
6462 | ||
6463 | static enum rtx_code | |
6464 | get_rtx_code (enum tree_code tcode, bool unsignedp) | |
6465 | { | |
6466 | enum rtx_code code; | |
6467 | switch (tcode) | |
6468 | { | |
6469 | case EQ_EXPR: | |
6470 | code = EQ; | |
6471 | break; | |
6472 | case NE_EXPR: | |
6473 | code = NE; | |
6474 | break; | |
6475 | case LT_EXPR: | |
6476 | code = unsignedp ? LTU : LT; | |
6477 | break; | |
6478 | case LE_EXPR: | |
6479 | code = unsignedp ? LEU : LE; | |
6480 | break; | |
6481 | case GT_EXPR: | |
6482 | code = unsignedp ? GTU : GT; | |
6483 | break; | |
6484 | case GE_EXPR: | |
6485 | code = unsignedp ? GEU : GE; | |
6486 | break; | |
c414ac1d | 6487 | |
7ce67fbe DP |
6488 | case UNORDERED_EXPR: |
6489 | code = UNORDERED; | |
6490 | break; | |
6491 | case ORDERED_EXPR: | |
6492 | code = ORDERED; | |
6493 | break; | |
6494 | case UNLT_EXPR: | |
6495 | code = UNLT; | |
6496 | break; | |
6497 | case UNLE_EXPR: | |
6498 | code = UNLE; | |
6499 | break; | |
6500 | case UNGT_EXPR: | |
6501 | code = UNGT; | |
6502 | break; | |
6503 | case UNGE_EXPR: | |
6504 | code = UNGE; | |
6505 | break; | |
6506 | case UNEQ_EXPR: | |
6507 | code = UNEQ; | |
6508 | break; | |
6509 | case LTGT_EXPR: | |
6510 | code = LTGT; | |
6511 | break; | |
6512 | ||
6513 | default: | |
e3feb571 | 6514 | gcc_unreachable (); |
7ce67fbe DP |
6515 | } |
6516 | return code; | |
6517 | } | |
6518 | ||
6519 | /* Return comparison rtx for COND. Use UNSIGNEDP to select signed or | |
6520 | unsigned operators. Do not generate compare instruction. */ | |
6521 | ||
6522 | static rtx | |
e6ed43b0 MG |
6523 | vector_compare_rtx (enum tree_code tcode, tree t_op0, tree t_op1, |
6524 | bool unsignedp, enum insn_code icode) | |
7ce67fbe | 6525 | { |
a5c7d693 | 6526 | struct expand_operand ops[2]; |
7ce67fbe | 6527 | rtx rtx_op0, rtx_op1; |
e6ed43b0 | 6528 | enum rtx_code rcode = get_rtx_code (tcode, unsignedp); |
7ce67fbe | 6529 | |
e6ed43b0 | 6530 | gcc_assert (TREE_CODE_CLASS (tcode) == tcc_comparison); |
c414ac1d | 6531 | |
7ce67fbe | 6532 | /* Expand operands. */ |
49452c07 UB |
6533 | rtx_op0 = expand_expr (t_op0, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op0)), |
6534 | EXPAND_STACK_PARM); | |
6535 | rtx_op1 = expand_expr (t_op1, NULL_RTX, TYPE_MODE (TREE_TYPE (t_op1)), | |
6536 | EXPAND_STACK_PARM); | |
7ce67fbe | 6537 | |
a5c7d693 RS |
6538 | create_input_operand (&ops[0], rtx_op0, GET_MODE (rtx_op0)); |
6539 | create_input_operand (&ops[1], rtx_op1, GET_MODE (rtx_op1)); | |
6540 | if (!maybe_legitimize_operands (icode, 4, 2, ops)) | |
6541 | gcc_unreachable (); | |
6542 | return gen_rtx_fmt_ee (rcode, VOIDmode, ops[0].value, ops[1].value); | |
7ce67fbe DP |
6543 | } |
6544 | ||
2205ed25 | 6545 | /* Return true if VEC_PERM_EXPR can be expanded using SIMD extensions |
2635892a | 6546 | of the CPU. SEL may be NULL, which stands for an unknown constant. */ |
d7943c8b | 6547 | |
f90e8e2e | 6548 | bool |
22e4dee7 RH |
6549 | can_vec_perm_p (enum machine_mode mode, bool variable, |
6550 | const unsigned char *sel) | |
f90e8e2e | 6551 | { |
22e4dee7 | 6552 | enum machine_mode qimode; |
d7943c8b RH |
6553 | |
6554 | /* If the target doesn't implement a vector mode for the vector type, | |
6555 | then no operations are supported. */ | |
6556 | if (!VECTOR_MODE_P (mode)) | |
6557 | return false; | |
f90e8e2e | 6558 | |
22e4dee7 | 6559 | if (!variable) |
d7943c8b RH |
6560 | { |
6561 | if (direct_optab_handler (vec_perm_const_optab, mode) != CODE_FOR_nothing | |
22e4dee7 RH |
6562 | && (sel == NULL |
6563 | || targetm.vectorize.vec_perm_const_ok == NULL | |
6564 | || targetm.vectorize.vec_perm_const_ok (mode, sel))) | |
d7943c8b RH |
6565 | return true; |
6566 | } | |
6567 | ||
6568 | if (direct_optab_handler (vec_perm_optab, mode) != CODE_FOR_nothing) | |
f90e8e2e AS |
6569 | return true; |
6570 | ||
d7943c8b | 6571 | /* We allow fallback to a QI vector mode, and adjust the mask. */ |
22e4dee7 RH |
6572 | if (GET_MODE_INNER (mode) == QImode) |
6573 | return false; | |
d7943c8b RH |
6574 | qimode = mode_for_vector (QImode, GET_MODE_SIZE (mode)); |
6575 | if (!VECTOR_MODE_P (qimode)) | |
6576 | return false; | |
6577 | ||
6578 | /* ??? For completeness, we ought to check the QImode version of | |
6579 | vec_perm_const_optab. But all users of this implicit lowering | |
6580 | feature implement the variable vec_perm_optab. */ | |
6581 | if (direct_optab_handler (vec_perm_optab, qimode) == CODE_FOR_nothing) | |
f90e8e2e AS |
6582 | return false; |
6583 | ||
22e4dee7 | 6584 | /* In order to support the lowering of variable permutations, |
d7943c8b | 6585 | we need to support shifts and adds. */ |
22e4dee7 | 6586 | if (variable) |
d7943c8b RH |
6587 | { |
6588 | if (GET_MODE_UNIT_SIZE (mode) > 2 | |
6589 | && optab_handler (ashl_optab, mode) == CODE_FOR_nothing | |
6590 | && optab_handler (vashl_optab, mode) == CODE_FOR_nothing) | |
6591 | return false; | |
6592 | if (optab_handler (add_optab, qimode) == CODE_FOR_nothing) | |
6593 | return false; | |
6594 | } | |
6595 | ||
6596 | return true; | |
f90e8e2e AS |
6597 | } |
6598 | ||
22e4dee7 | 6599 | /* A subroutine of expand_vec_perm for expanding one vec_perm insn. */ |
d7943c8b RH |
6600 | |
6601 | static rtx | |
22e4dee7 RH |
6602 | expand_vec_perm_1 (enum insn_code icode, rtx target, |
6603 | rtx v0, rtx v1, rtx sel) | |
f90e8e2e | 6604 | { |
d7943c8b RH |
6605 | enum machine_mode tmode = GET_MODE (target); |
6606 | enum machine_mode smode = GET_MODE (sel); | |
f90e8e2e | 6607 | struct expand_operand ops[4]; |
f90e8e2e | 6608 | |
d7943c8b RH |
6609 | create_output_operand (&ops[0], target, tmode); |
6610 | create_input_operand (&ops[3], sel, smode); | |
f90e8e2e | 6611 | |
d7943c8b RH |
6612 | /* Make an effort to preserve v0 == v1. The target expander is able to |
6613 | rely on this to determine if we're permuting a single input operand. */ | |
6614 | if (rtx_equal_p (v0, v1)) | |
f90e8e2e | 6615 | { |
d7943c8b RH |
6616 | if (!insn_operand_matches (icode, 1, v0)) |
6617 | v0 = force_reg (tmode, v0); | |
6618 | gcc_checking_assert (insn_operand_matches (icode, 1, v0)); | |
6619 | gcc_checking_assert (insn_operand_matches (icode, 2, v0)); | |
f90e8e2e | 6620 | |
d7943c8b RH |
6621 | create_fixed_operand (&ops[1], v0); |
6622 | create_fixed_operand (&ops[2], v0); | |
6623 | } | |
6624 | else | |
6625 | { | |
6626 | create_input_operand (&ops[1], v0, tmode); | |
6627 | create_input_operand (&ops[2], v1, tmode); | |
6628 | } | |
f90e8e2e | 6629 | |
d7943c8b RH |
6630 | if (maybe_expand_insn (icode, 4, ops)) |
6631 | return ops[0].value; | |
6632 | return NULL_RTX; | |
6633 | } | |
f90e8e2e | 6634 | |
22e4dee7 RH |
6635 | /* Generate instructions for vec_perm optab given its mode |
6636 | and three operands. */ | |
6637 | ||
d7943c8b | 6638 | rtx |
22e4dee7 | 6639 | expand_vec_perm (enum machine_mode mode, rtx v0, rtx v1, rtx sel, rtx target) |
d7943c8b RH |
6640 | { |
6641 | enum insn_code icode; | |
d7943c8b | 6642 | enum machine_mode qimode; |
d7943c8b | 6643 | unsigned int i, w, e, u; |
4cb110fb | 6644 | rtx tmp, sel_qi = NULL; |
22e4dee7 | 6645 | rtvec vec; |
d7943c8b | 6646 | |
22e4dee7 | 6647 | if (!target || GET_MODE (target) != mode) |
d7943c8b | 6648 | target = gen_reg_rtx (mode); |
22e4dee7 RH |
6649 | |
6650 | w = GET_MODE_SIZE (mode); | |
6651 | e = GET_MODE_NUNITS (mode); | |
6652 | u = GET_MODE_UNIT_SIZE (mode); | |
6653 | ||
6654 | /* Set QIMODE to a different vector mode with byte elements. | |
6655 | If no such mode, or if MODE already has byte elements, use VOIDmode. */ | |
6656 | qimode = VOIDmode; | |
6657 | if (GET_MODE_INNER (mode) != QImode) | |
6658 | { | |
6659 | qimode = mode_for_vector (QImode, w); | |
6660 | if (!VECTOR_MODE_P (qimode)) | |
6661 | qimode = VOIDmode; | |
6662 | } | |
f90e8e2e | 6663 | |
d7943c8b | 6664 | /* If the input is a constant, expand it specially. */ |
ccdfb0e2 RH |
6665 | gcc_assert (GET_MODE_CLASS (GET_MODE (sel)) == MODE_VECTOR_INT); |
6666 | if (GET_CODE (sel) == CONST_VECTOR) | |
d7943c8b RH |
6667 | { |
6668 | icode = direct_optab_handler (vec_perm_const_optab, mode); | |
22e4dee7 RH |
6669 | if (icode != CODE_FOR_nothing) |
6670 | { | |
6671 | tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); | |
6672 | if (tmp) | |
6673 | return tmp; | |
6674 | } | |
6675 | ||
6676 | /* Fall back to a constant byte-based permutation. */ | |
6677 | if (qimode != VOIDmode) | |
6678 | { | |
4cb110fb RH |
6679 | vec = rtvec_alloc (w); |
6680 | for (i = 0; i < e; ++i) | |
22e4dee7 | 6681 | { |
4cb110fb | 6682 | unsigned int j, this_e; |
22e4dee7 | 6683 | |
ccdfb0e2 | 6684 | this_e = INTVAL (CONST_VECTOR_ELT (sel, i)); |
4cb110fb RH |
6685 | this_e &= 2 * e - 1; |
6686 | this_e *= u; | |
22e4dee7 | 6687 | |
4cb110fb RH |
6688 | for (j = 0; j < u; ++j) |
6689 | RTVEC_ELT (vec, i * u + j) = GEN_INT (this_e + j); | |
6690 | } | |
6691 | sel_qi = gen_rtx_CONST_VECTOR (qimode, vec); | |
22e4dee7 | 6692 | |
4cb110fb RH |
6693 | icode = direct_optab_handler (vec_perm_const_optab, qimode); |
6694 | if (icode != CODE_FOR_nothing) | |
6695 | { | |
d8c84975 JJ |
6696 | tmp = mode != qimode ? gen_reg_rtx (qimode) : target; |
6697 | tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), | |
22e4dee7 RH |
6698 | gen_lowpart (qimode, v1), sel_qi); |
6699 | if (tmp) | |
6700 | return gen_lowpart (mode, tmp); | |
6701 | } | |
6702 | } | |
f90e8e2e AS |
6703 | } |
6704 | ||
22e4dee7 | 6705 | /* Otherwise expand as a fully variable permuation. */ |
2205ed25 | 6706 | icode = direct_optab_handler (vec_perm_optab, mode); |
22e4dee7 RH |
6707 | if (icode != CODE_FOR_nothing) |
6708 | { | |
6709 | tmp = expand_vec_perm_1 (icode, target, v0, v1, sel); | |
6710 | if (tmp) | |
6711 | return tmp; | |
6712 | } | |
d7943c8b RH |
6713 | |
6714 | /* As a special case to aid several targets, lower the element-based | |
6715 | permutation to a byte-based permutation and try again. */ | |
22e4dee7 | 6716 | if (qimode == VOIDmode) |
d7943c8b | 6717 | return NULL_RTX; |
d7943c8b | 6718 | icode = direct_optab_handler (vec_perm_optab, qimode); |
f90e8e2e | 6719 | if (icode == CODE_FOR_nothing) |
d7943c8b | 6720 | return NULL_RTX; |
f90e8e2e | 6721 | |
4cb110fb RH |
6722 | if (sel_qi == NULL) |
6723 | { | |
6724 | /* Multiply each element by its byte size. */ | |
6725 | enum machine_mode selmode = GET_MODE (sel); | |
6726 | if (u == 2) | |
6727 | sel = expand_simple_binop (selmode, PLUS, sel, sel, | |
6728 | sel, 0, OPTAB_DIRECT); | |
6729 | else | |
6730 | sel = expand_simple_binop (selmode, ASHIFT, sel, | |
6731 | GEN_INT (exact_log2 (u)), | |
6732 | sel, 0, OPTAB_DIRECT); | |
6733 | gcc_assert (sel != NULL); | |
6734 | ||
6735 | /* Broadcast the low byte each element into each of its bytes. */ | |
6736 | vec = rtvec_alloc (w); | |
6737 | for (i = 0; i < w; ++i) | |
6738 | { | |
6739 | int this_e = i / u * u; | |
6740 | if (BYTES_BIG_ENDIAN) | |
6741 | this_e += u - 1; | |
6742 | RTVEC_ELT (vec, i) = GEN_INT (this_e); | |
6743 | } | |
6744 | tmp = gen_rtx_CONST_VECTOR (qimode, vec); | |
6745 | sel = gen_lowpart (qimode, sel); | |
b96d19ff | 6746 | sel = expand_vec_perm (qimode, sel, sel, tmp, NULL); |
4cb110fb RH |
6747 | gcc_assert (sel != NULL); |
6748 | ||
6749 | /* Add the byte offset to each byte element. */ | |
6750 | /* Note that the definition of the indicies here is memory ordering, | |
6751 | so there should be no difference between big and little endian. */ | |
6752 | vec = rtvec_alloc (w); | |
6753 | for (i = 0; i < w; ++i) | |
6754 | RTVEC_ELT (vec, i) = GEN_INT (i % u); | |
6755 | tmp = gen_rtx_CONST_VECTOR (qimode, vec); | |
6756 | sel_qi = expand_simple_binop (qimode, PLUS, sel, tmp, | |
6757 | sel, 0, OPTAB_DIRECT); | |
6758 | gcc_assert (sel_qi != NULL); | |
6759 | } | |
22e4dee7 | 6760 | |
d8c84975 JJ |
6761 | tmp = mode != qimode ? gen_reg_rtx (qimode) : target; |
6762 | tmp = expand_vec_perm_1 (icode, tmp, gen_lowpart (qimode, v0), | |
4cb110fb | 6763 | gen_lowpart (qimode, v1), sel_qi); |
22e4dee7 RH |
6764 | if (tmp) |
6765 | tmp = gen_lowpart (mode, tmp); | |
6766 | return tmp; | |
f90e8e2e AS |
6767 | } |
6768 | ||
e9e1d143 RG |
6769 | /* Return insn code for a conditional operator with a comparison in |
6770 | mode CMODE, unsigned if UNS is true, resulting in a value of mode VMODE. */ | |
c414ac1d EC |
6771 | |
6772 | static inline enum insn_code | |
e9e1d143 | 6773 | get_vcond_icode (enum machine_mode vmode, enum machine_mode cmode, bool uns) |
7ce67fbe DP |
6774 | { |
6775 | enum insn_code icode = CODE_FOR_nothing; | |
e9e1d143 RG |
6776 | if (uns) |
6777 | icode = convert_optab_handler (vcondu_optab, vmode, cmode); | |
7ce67fbe | 6778 | else |
e9e1d143 | 6779 | icode = convert_optab_handler (vcond_optab, vmode, cmode); |
7ce67fbe DP |
6780 | return icode; |
6781 | } | |
6782 | ||
6783 | /* Return TRUE iff, appropriate vector insns are available | |
e9e1d143 RG |
6784 | for vector cond expr with vector type VALUE_TYPE and a comparison |
6785 | with operand vector types in CMP_OP_TYPE. */ | |
7ce67fbe DP |
6786 | |
6787 | bool | |
e9e1d143 | 6788 | expand_vec_cond_expr_p (tree value_type, tree cmp_op_type) |
7ce67fbe | 6789 | { |
e9e1d143 RG |
6790 | enum machine_mode value_mode = TYPE_MODE (value_type); |
6791 | enum machine_mode cmp_op_mode = TYPE_MODE (cmp_op_type); | |
6792 | if (GET_MODE_SIZE (value_mode) != GET_MODE_SIZE (cmp_op_mode) | |
6793 | || GET_MODE_NUNITS (value_mode) != GET_MODE_NUNITS (cmp_op_mode) | |
6794 | || get_vcond_icode (TYPE_MODE (value_type), TYPE_MODE (cmp_op_type), | |
6795 | TYPE_UNSIGNED (cmp_op_type)) == CODE_FOR_nothing) | |
7ce67fbe DP |
6796 | return false; |
6797 | return true; | |
6798 | } | |
6799 | ||
8e7aa1f9 MM |
6800 | /* Generate insns for a VEC_COND_EXPR, given its TYPE and its |
6801 | three operands. */ | |
7ce67fbe DP |
6802 | |
6803 | rtx | |
8e7aa1f9 MM |
6804 | expand_vec_cond_expr (tree vec_cond_type, tree op0, tree op1, tree op2, |
6805 | rtx target) | |
7ce67fbe | 6806 | { |
a5c7d693 | 6807 | struct expand_operand ops[6]; |
7ce67fbe | 6808 | enum insn_code icode; |
a5c7d693 | 6809 | rtx comparison, rtx_op1, rtx_op2; |
8e7aa1f9 | 6810 | enum machine_mode mode = TYPE_MODE (vec_cond_type); |
e9e1d143 RG |
6811 | enum machine_mode cmp_op_mode; |
6812 | bool unsignedp; | |
e6ed43b0 MG |
6813 | tree op0a, op0b; |
6814 | enum tree_code tcode; | |
e9e1d143 | 6815 | |
e6ed43b0 MG |
6816 | if (COMPARISON_CLASS_P (op0)) |
6817 | { | |
6818 | op0a = TREE_OPERAND (op0, 0); | |
6819 | op0b = TREE_OPERAND (op0, 1); | |
6820 | tcode = TREE_CODE (op0); | |
6821 | } | |
6822 | else | |
6823 | { | |
6824 | /* Fake op0 < 0. */ | |
6825 | gcc_assert (!TYPE_UNSIGNED (TREE_TYPE (op0))); | |
6826 | op0a = op0; | |
6827 | op0b = build_zero_cst (TREE_TYPE (op0)); | |
6828 | tcode = LT_EXPR; | |
6829 | } | |
6830 | unsignedp = TYPE_UNSIGNED (TREE_TYPE (op0a)); | |
6831 | cmp_op_mode = TYPE_MODE (TREE_TYPE (op0a)); | |
e9e1d143 | 6832 | |
e9e1d143 RG |
6833 | |
6834 | gcc_assert (GET_MODE_SIZE (mode) == GET_MODE_SIZE (cmp_op_mode) | |
6835 | && GET_MODE_NUNITS (mode) == GET_MODE_NUNITS (cmp_op_mode)); | |
7ce67fbe | 6836 | |
e9e1d143 | 6837 | icode = get_vcond_icode (mode, cmp_op_mode, unsignedp); |
7ce67fbe DP |
6838 | if (icode == CODE_FOR_nothing) |
6839 | return 0; | |
6840 | ||
e6ed43b0 | 6841 | comparison = vector_compare_rtx (tcode, op0a, op0b, unsignedp, icode); |
8e7aa1f9 | 6842 | rtx_op1 = expand_normal (op1); |
8e7aa1f9 | 6843 | rtx_op2 = expand_normal (op2); |
7ce67fbe | 6844 | |
a5c7d693 RS |
6845 | create_output_operand (&ops[0], target, mode); |
6846 | create_input_operand (&ops[1], rtx_op1, mode); | |
6847 | create_input_operand (&ops[2], rtx_op2, mode); | |
6848 | create_fixed_operand (&ops[3], comparison); | |
6849 | create_fixed_operand (&ops[4], XEXP (comparison, 0)); | |
6850 | create_fixed_operand (&ops[5], XEXP (comparison, 1)); | |
6851 | expand_insn (icode, 6, ops); | |
6852 | return ops[0].value; | |
7ce67fbe | 6853 | } |
48ae6c13 | 6854 | |
00f07b86 RH |
6855 | /* Return non-zero if a highpart multiply is supported of can be synthisized. |
6856 | For the benefit of expand_mult_highpart, the return value is 1 for direct, | |
6857 | 2 for even/odd widening, and 3 for hi/lo widening. */ | |
6858 | ||
6859 | int | |
6860 | can_mult_highpart_p (enum machine_mode mode, bool uns_p) | |
6861 | { | |
6862 | optab op; | |
6863 | unsigned char *sel; | |
6864 | unsigned i, nunits; | |
6865 | ||
6866 | op = uns_p ? umul_highpart_optab : smul_highpart_optab; | |
6867 | if (optab_handler (op, mode) != CODE_FOR_nothing) | |
6868 | return 1; | |
6869 | ||
6870 | /* If the mode is an integral vector, synth from widening operations. */ | |
6871 | if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT) | |
6872 | return 0; | |
6873 | ||
6874 | nunits = GET_MODE_NUNITS (mode); | |
6875 | sel = XALLOCAVEC (unsigned char, nunits); | |
6876 | ||
6877 | op = uns_p ? vec_widen_umult_even_optab : vec_widen_smult_even_optab; | |
6878 | if (optab_handler (op, mode) != CODE_FOR_nothing) | |
6879 | { | |
6880 | op = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab; | |
6881 | if (optab_handler (op, mode) != CODE_FOR_nothing) | |
6882 | { | |
6883 | for (i = 0; i < nunits; ++i) | |
6884 | sel[i] = !BYTES_BIG_ENDIAN + (i & ~1) + ((i & 1) ? nunits : 0); | |
6885 | if (can_vec_perm_p (mode, false, sel)) | |
6886 | return 2; | |
6887 | } | |
6888 | } | |
6889 | ||
6890 | op = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; | |
6891 | if (optab_handler (op, mode) != CODE_FOR_nothing) | |
6892 | { | |
6893 | op = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; | |
6894 | if (optab_handler (op, mode) != CODE_FOR_nothing) | |
6895 | { | |
6896 | for (i = 0; i < nunits; ++i) | |
6897 | sel[i] = 2 * i + (BYTES_BIG_ENDIAN ? 0 : 1); | |
6898 | if (can_vec_perm_p (mode, false, sel)) | |
6899 | return 3; | |
6900 | } | |
6901 | } | |
6902 | ||
6903 | return 0; | |
6904 | } | |
6905 | ||
6906 | /* Expand a highpart multiply. */ | |
6907 | ||
6908 | rtx | |
6909 | expand_mult_highpart (enum machine_mode mode, rtx op0, rtx op1, | |
6910 | rtx target, bool uns_p) | |
6911 | { | |
6912 | struct expand_operand eops[3]; | |
6913 | enum insn_code icode; | |
6914 | int method, i, nunits; | |
6915 | enum machine_mode wmode; | |
6916 | rtx m1, m2, perm; | |
6917 | optab tab1, tab2; | |
6918 | rtvec v; | |
6919 | ||
6920 | method = can_mult_highpart_p (mode, uns_p); | |
6921 | switch (method) | |
6922 | { | |
6923 | case 0: | |
6924 | return NULL_RTX; | |
6925 | case 1: | |
6926 | tab1 = uns_p ? umul_highpart_optab : smul_highpart_optab; | |
6927 | return expand_binop (mode, tab1, op0, op1, target, uns_p, | |
6928 | OPTAB_LIB_WIDEN); | |
6929 | case 2: | |
6930 | tab1 = uns_p ? vec_widen_umult_even_optab : vec_widen_smult_even_optab; | |
6931 | tab2 = uns_p ? vec_widen_umult_odd_optab : vec_widen_smult_odd_optab; | |
6932 | break; | |
6933 | case 3: | |
6934 | tab1 = uns_p ? vec_widen_umult_lo_optab : vec_widen_smult_lo_optab; | |
6935 | tab2 = uns_p ? vec_widen_umult_hi_optab : vec_widen_smult_hi_optab; | |
6936 | if (BYTES_BIG_ENDIAN) | |
6937 | { | |
6938 | optab t = tab1; | |
6939 | tab1 = tab2; | |
6940 | tab2 = t; | |
6941 | } | |
6942 | break; | |
6943 | default: | |
6944 | gcc_unreachable (); | |
6945 | } | |
6946 | ||
6947 | icode = optab_handler (tab1, mode); | |
6948 | nunits = GET_MODE_NUNITS (mode); | |
6949 | wmode = insn_data[icode].operand[0].mode; | |
6950 | gcc_checking_assert (2 * GET_MODE_NUNITS (wmode) == nunits); | |
6951 | gcc_checking_assert (GET_MODE_SIZE (wmode) == GET_MODE_SIZE (mode)); | |
6952 | ||
6953 | create_output_operand (&eops[0], gen_reg_rtx (wmode), wmode); | |
6954 | create_input_operand (&eops[1], op0, mode); | |
6955 | create_input_operand (&eops[2], op1, mode); | |
6956 | expand_insn (icode, 3, eops); | |
6957 | m1 = gen_lowpart (mode, eops[0].value); | |
6958 | ||
6959 | create_output_operand (&eops[0], gen_reg_rtx (wmode), wmode); | |
6960 | create_input_operand (&eops[1], op0, mode); | |
6961 | create_input_operand (&eops[2], op1, mode); | |
6962 | expand_insn (optab_handler (tab2, mode), 3, eops); | |
6963 | m2 = gen_lowpart (mode, eops[0].value); | |
6964 | ||
6965 | v = rtvec_alloc (nunits); | |
6966 | if (method == 2) | |
6967 | { | |
6968 | for (i = 0; i < nunits; ++i) | |
6969 | RTVEC_ELT (v, i) = GEN_INT (!BYTES_BIG_ENDIAN + (i & ~1) | |
6970 | + ((i & 1) ? nunits : 0)); | |
6971 | } | |
6972 | else | |
6973 | { | |
6974 | for (i = 0; i < nunits; ++i) | |
6975 | RTVEC_ELT (v, i) = GEN_INT (2 * i + (BYTES_BIG_ENDIAN ? 0 : 1)); | |
6976 | } | |
6977 | perm = gen_rtx_CONST_VECTOR (mode, v); | |
6978 | ||
6979 | return expand_vec_perm (mode, m1, m2, perm, target); | |
6980 | } | |
5ce9450f JJ |
6981 | |
6982 | /* Return true if target supports vector masked load/store for mode. */ | |
6983 | bool | |
6984 | can_vec_mask_load_store_p (enum machine_mode mode, bool is_load) | |
6985 | { | |
6986 | optab op = is_load ? maskload_optab : maskstore_optab; | |
6987 | enum machine_mode vmode; | |
6988 | unsigned int vector_sizes; | |
6989 | ||
6990 | /* If mode is vector mode, check it directly. */ | |
6991 | if (VECTOR_MODE_P (mode)) | |
6992 | return optab_handler (op, mode) != CODE_FOR_nothing; | |
6993 | ||
6994 | /* Otherwise, return true if there is some vector mode with | |
6995 | the mask load/store supported. */ | |
6996 | ||
6997 | /* See if there is any chance the mask load or store might be | |
6998 | vectorized. If not, punt. */ | |
6999 | vmode = targetm.vectorize.preferred_simd_mode (mode); | |
7000 | if (!VECTOR_MODE_P (vmode)) | |
7001 | return false; | |
7002 | ||
7003 | if (optab_handler (op, vmode) != CODE_FOR_nothing) | |
7004 | return true; | |
7005 | ||
7006 | vector_sizes = targetm.vectorize.autovectorize_vector_sizes (); | |
7007 | while (vector_sizes != 0) | |
7008 | { | |
7009 | unsigned int cur = 1 << floor_log2 (vector_sizes); | |
7010 | vector_sizes &= ~cur; | |
7011 | if (cur <= GET_MODE_SIZE (mode)) | |
7012 | continue; | |
7013 | vmode = mode_for_vector (mode, cur / GET_MODE_SIZE (mode)); | |
7014 | if (VECTOR_MODE_P (vmode) | |
7015 | && optab_handler (op, vmode) != CODE_FOR_nothing) | |
7016 | return true; | |
7017 | } | |
7018 | return false; | |
7019 | } | |
48ae6c13 | 7020 | \f |
86951993 | 7021 | /* Return true if there is a compare_and_swap pattern. */ |
48ae6c13 | 7022 | |
86951993 | 7023 | bool |
cedb4a1a | 7024 | can_compare_and_swap_p (enum machine_mode mode, bool allow_libcall) |
48ae6c13 | 7025 | { |
86951993 | 7026 | enum insn_code icode; |
48ae6c13 | 7027 | |
86951993 AM |
7028 | /* Check for __atomic_compare_and_swap. */ |
7029 | icode = direct_optab_handler (atomic_compare_and_swap_optab, mode); | |
7030 | if (icode != CODE_FOR_nothing) | |
cedb4a1a RH |
7031 | return true; |
7032 | ||
7033 | /* Check for __sync_compare_and_swap. */ | |
7034 | icode = optab_handler (sync_compare_and_swap_optab, mode); | |
7035 | if (icode != CODE_FOR_nothing) | |
7036 | return true; | |
7037 | if (allow_libcall && optab_libfunc (sync_compare_and_swap_optab, mode)) | |
7038 | return true; | |
48ae6c13 | 7039 | |
86951993 AM |
7040 | /* No inline compare and swap. */ |
7041 | return false; | |
48ae6c13 RH |
7042 | } |
7043 | ||
05409788 RH |
7044 | /* Return true if an atomic exchange can be performed. */ |
7045 | ||
7046 | bool | |
7047 | can_atomic_exchange_p (enum machine_mode mode, bool allow_libcall) | |
7048 | { | |
7049 | enum insn_code icode; | |
7050 | ||
7051 | /* Check for __atomic_exchange. */ | |
7052 | icode = direct_optab_handler (atomic_exchange_optab, mode); | |
7053 | if (icode != CODE_FOR_nothing) | |
7054 | return true; | |
7055 | ||
7056 | /* Don't check __sync_test_and_set, as on some platforms that | |
7057 | has reduced functionality. Targets that really do support | |
7058 | a proper exchange should simply be updated to the __atomics. */ | |
7059 | ||
7060 | return can_compare_and_swap_p (mode, allow_libcall); | |
7061 | } | |
7062 | ||
7063 | ||
4a77c72b PB |
7064 | /* Helper function to find the MODE_CC set in a sync_compare_and_swap |
7065 | pattern. */ | |
7066 | ||
7067 | static void | |
7068 | find_cc_set (rtx x, const_rtx pat, void *data) | |
7069 | { | |
7070 | if (REG_P (x) && GET_MODE_CLASS (GET_MODE (x)) == MODE_CC | |
7071 | && GET_CODE (pat) == SET) | |
7072 | { | |
7073 | rtx *p_cc_reg = (rtx *) data; | |
7074 | gcc_assert (!*p_cc_reg); | |
7075 | *p_cc_reg = x; | |
7076 | } | |
7077 | } | |
7078 | ||
48ae6c13 RH |
7079 | /* This is a helper function for the other atomic operations. This function |
7080 | emits a loop that contains SEQ that iterates until a compare-and-swap | |
7081 | operation at the end succeeds. MEM is the memory to be modified. SEQ is | |
7082 | a set of instructions that takes a value from OLD_REG as an input and | |
7083 | produces a value in NEW_REG as an output. Before SEQ, OLD_REG will be | |
7084 | set to the current contents of MEM. After SEQ, a compare-and-swap will | |
7085 | attempt to update MEM with NEW_REG. The function returns true when the | |
7086 | loop was generated successfully. */ | |
7087 | ||
7088 | static bool | |
7089 | expand_compare_and_swap_loop (rtx mem, rtx old_reg, rtx new_reg, rtx seq) | |
7090 | { | |
7091 | enum machine_mode mode = GET_MODE (mem); | |
86951993 | 7092 | rtx label, cmp_reg, success, oldval; |
48ae6c13 RH |
7093 | |
7094 | /* The loop we want to generate looks like | |
7095 | ||
81ba4f39 | 7096 | cmp_reg = mem; |
48ae6c13 | 7097 | label: |
81ba4f39 | 7098 | old_reg = cmp_reg; |
48ae6c13 | 7099 | seq; |
86951993 AM |
7100 | (success, cmp_reg) = compare-and-swap(mem, old_reg, new_reg) |
7101 | if (success) | |
48ae6c13 RH |
7102 | goto label; |
7103 | ||
7104 | Note that we only do the plain load from memory once. Subsequent | |
7105 | iterations use the value loaded by the compare-and-swap pattern. */ | |
7106 | ||
7107 | label = gen_label_rtx (); | |
81ba4f39 | 7108 | cmp_reg = gen_reg_rtx (mode); |
48ae6c13 | 7109 | |
81ba4f39 | 7110 | emit_move_insn (cmp_reg, mem); |
48ae6c13 | 7111 | emit_label (label); |
81ba4f39 | 7112 | emit_move_insn (old_reg, cmp_reg); |
48ae6c13 RH |
7113 | if (seq) |
7114 | emit_insn (seq); | |
7115 | ||
86951993 AM |
7116 | success = NULL_RTX; |
7117 | oldval = cmp_reg; | |
7118 | if (!expand_atomic_compare_and_swap (&success, &oldval, mem, old_reg, | |
7119 | new_reg, false, MEMMODEL_SEQ_CST, | |
7120 | MEMMODEL_RELAXED)) | |
4a77c72b | 7121 | return false; |
48ae6c13 | 7122 | |
86951993 AM |
7123 | if (oldval != cmp_reg) |
7124 | emit_move_insn (cmp_reg, oldval); | |
48ae6c13 | 7125 | |
a4da41e1 | 7126 | /* Mark this jump predicted not taken. */ |
86951993 | 7127 | emit_cmp_and_jump_insns (success, const0_rtx, EQ, const0_rtx, |
a4da41e1 | 7128 | GET_MODE (success), 1, label, 0); |
86951993 AM |
7129 | return true; |
7130 | } | |
7131 | ||
7132 | ||
744accb2 AM |
7133 | /* This function tries to emit an atomic_exchange intruction. VAL is written |
7134 | to *MEM using memory model MODEL. The previous contents of *MEM are returned, | |
7135 | using TARGET if possible. */ | |
7136 | ||
7137 | static rtx | |
7138 | maybe_emit_atomic_exchange (rtx target, rtx mem, rtx val, enum memmodel model) | |
86951993 AM |
7139 | { |
7140 | enum machine_mode mode = GET_MODE (mem); | |
7141 | enum insn_code icode; | |
86951993 AM |
7142 | |
7143 | /* If the target supports the exchange directly, great. */ | |
7144 | icode = direct_optab_handler (atomic_exchange_optab, mode); | |
7145 | if (icode != CODE_FOR_nothing) | |
4a77c72b | 7146 | { |
86951993 AM |
7147 | struct expand_operand ops[4]; |
7148 | ||
7149 | create_output_operand (&ops[0], target, mode); | |
7150 | create_fixed_operand (&ops[1], mem); | |
464046a6 | 7151 | create_input_operand (&ops[2], val, mode); |
86951993 AM |
7152 | create_integer_operand (&ops[3], model); |
7153 | if (maybe_expand_insn (icode, 4, ops)) | |
7154 | return ops[0].value; | |
4a77c72b | 7155 | } |
86951993 | 7156 | |
744accb2 AM |
7157 | return NULL_RTX; |
7158 | } | |
7159 | ||
7160 | /* This function tries to implement an atomic exchange operation using | |
7161 | __sync_lock_test_and_set. VAL is written to *MEM using memory model MODEL. | |
7162 | The previous contents of *MEM are returned, using TARGET if possible. | |
7163 | Since this instructionn is an acquire barrier only, stronger memory | |
7164 | models may require additional barriers to be emitted. */ | |
86951993 | 7165 | |
744accb2 AM |
7166 | static rtx |
7167 | maybe_emit_sync_lock_test_and_set (rtx target, rtx mem, rtx val, | |
7168 | enum memmodel model) | |
7169 | { | |
7170 | enum machine_mode mode = GET_MODE (mem); | |
7171 | enum insn_code icode; | |
7172 | rtx last_insn = get_last_insn (); | |
7173 | ||
7174 | icode = optab_handler (sync_lock_test_and_set_optab, mode); | |
7175 | ||
7176 | /* Legacy sync_lock_test_and_set is an acquire barrier. If the pattern | |
7177 | exists, and the memory model is stronger than acquire, add a release | |
7178 | barrier before the instruction. */ | |
86951993 | 7179 | |
88e784e6 UB |
7180 | if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST |
7181 | || (model & MEMMODEL_MASK) == MEMMODEL_RELEASE | |
7182 | || (model & MEMMODEL_MASK) == MEMMODEL_ACQ_REL) | |
744accb2 AM |
7183 | expand_mem_thread_fence (model); |
7184 | ||
7185 | if (icode != CODE_FOR_nothing) | |
4a77c72b | 7186 | { |
744accb2 AM |
7187 | struct expand_operand ops[3]; |
7188 | create_output_operand (&ops[0], target, mode); | |
7189 | create_fixed_operand (&ops[1], mem); | |
464046a6 | 7190 | create_input_operand (&ops[2], val, mode); |
744accb2 AM |
7191 | if (maybe_expand_insn (icode, 3, ops)) |
7192 | return ops[0].value; | |
7193 | } | |
86951993 | 7194 | |
744accb2 AM |
7195 | /* If an external test-and-set libcall is provided, use that instead of |
7196 | any external compare-and-swap that we might get from the compare-and- | |
7197 | swap-loop expansion later. */ | |
7198 | if (!can_compare_and_swap_p (mode, false)) | |
7199 | { | |
7200 | rtx libfunc = optab_libfunc (sync_lock_test_and_set_optab, mode); | |
7201 | if (libfunc != NULL) | |
0669295b | 7202 | { |
744accb2 AM |
7203 | rtx addr; |
7204 | ||
7205 | addr = convert_memory_address (ptr_mode, XEXP (mem, 0)); | |
fae67e1d | 7206 | return emit_library_call_value (libfunc, NULL_RTX, LCT_NORMAL, |
744accb2 AM |
7207 | mode, 2, addr, ptr_mode, |
7208 | val, mode); | |
0669295b | 7209 | } |
744accb2 | 7210 | } |
48ae6c13 | 7211 | |
744accb2 AM |
7212 | /* If the test_and_set can't be emitted, eliminate any barrier that might |
7213 | have been emitted. */ | |
7214 | delete_insns_since (last_insn); | |
7215 | return NULL_RTX; | |
7216 | } | |
cedb4a1a | 7217 | |
744accb2 AM |
7218 | /* This function tries to implement an atomic exchange operation using a |
7219 | compare_and_swap loop. VAL is written to *MEM. The previous contents of | |
7220 | *MEM are returned, using TARGET if possible. No memory model is required | |
7221 | since a compare_and_swap loop is seq-cst. */ | |
cedb4a1a | 7222 | |
744accb2 AM |
7223 | static rtx |
7224 | maybe_emit_compare_and_swap_exchange_loop (rtx target, rtx mem, rtx val) | |
7225 | { | |
7226 | enum machine_mode mode = GET_MODE (mem); | |
86951993 | 7227 | |
cedb4a1a | 7228 | if (can_compare_and_swap_p (mode, true)) |
86951993 AM |
7229 | { |
7230 | if (!target || !register_operand (target, mode)) | |
7231 | target = gen_reg_rtx (mode); | |
86951993 AM |
7232 | if (expand_compare_and_swap_loop (mem, target, val, NULL_RTX)) |
7233 | return target; | |
7234 | } | |
7235 | ||
7236 | return NULL_RTX; | |
7237 | } | |
7238 | ||
f8a27aa6 RH |
7239 | /* This function tries to implement an atomic test-and-set operation |
7240 | using the atomic_test_and_set instruction pattern. A boolean value | |
7241 | is returned from the operation, using TARGET if possible. */ | |
7242 | ||
744accb2 AM |
7243 | #ifndef HAVE_atomic_test_and_set |
7244 | #define HAVE_atomic_test_and_set 0 | |
f8a27aa6 | 7245 | #define CODE_FOR_atomic_test_and_set CODE_FOR_nothing |
744accb2 AM |
7246 | #endif |
7247 | ||
f8a27aa6 RH |
7248 | static rtx |
7249 | maybe_emit_atomic_test_and_set (rtx target, rtx mem, enum memmodel model) | |
7250 | { | |
7251 | enum machine_mode pat_bool_mode; | |
15e73e06 | 7252 | struct expand_operand ops[3]; |
f8a27aa6 RH |
7253 | |
7254 | if (!HAVE_atomic_test_and_set) | |
7255 | return NULL_RTX; | |
7256 | ||
42cf0609 RH |
7257 | /* While we always get QImode from __atomic_test_and_set, we get |
7258 | other memory modes from __sync_lock_test_and_set. Note that we | |
7259 | use no endian adjustment here. This matches the 4.6 behavior | |
7260 | in the Sparc backend. */ | |
15e73e06 RH |
7261 | gcc_checking_assert |
7262 | (insn_data[CODE_FOR_atomic_test_and_set].operand[1].mode == QImode); | |
42cf0609 RH |
7263 | if (GET_MODE (mem) != QImode) |
7264 | mem = adjust_address_nv (mem, QImode, 0); | |
f8a27aa6 | 7265 | |
15e73e06 RH |
7266 | pat_bool_mode = insn_data[CODE_FOR_atomic_test_and_set].operand[0].mode; |
7267 | create_output_operand (&ops[0], target, pat_bool_mode); | |
7268 | create_fixed_operand (&ops[1], mem); | |
7269 | create_integer_operand (&ops[2], model); | |
f8a27aa6 | 7270 | |
15e73e06 RH |
7271 | if (maybe_expand_insn (CODE_FOR_atomic_test_and_set, 3, ops)) |
7272 | return ops[0].value; | |
7273 | return NULL_RTX; | |
f8a27aa6 RH |
7274 | } |
7275 | ||
744accb2 AM |
7276 | /* This function expands the legacy _sync_lock test_and_set operation which is |
7277 | generally an atomic exchange. Some limited targets only allow the | |
7278 | constant 1 to be stored. This is an ACQUIRE operation. | |
7279 | ||
7280 | TARGET is an optional place to stick the return value. | |
7281 | MEM is where VAL is stored. */ | |
7282 | ||
7283 | rtx | |
7284 | expand_sync_lock_test_and_set (rtx target, rtx mem, rtx val) | |
7285 | { | |
7286 | rtx ret; | |
7287 | ||
7288 | /* Try an atomic_exchange first. */ | |
7289 | ret = maybe_emit_atomic_exchange (target, mem, val, MEMMODEL_ACQUIRE); | |
f8a27aa6 RH |
7290 | if (ret) |
7291 | return ret; | |
7292 | ||
7293 | ret = maybe_emit_sync_lock_test_and_set (target, mem, val, MEMMODEL_ACQUIRE); | |
7294 | if (ret) | |
7295 | return ret; | |
744accb2 | 7296 | |
f8a27aa6 RH |
7297 | ret = maybe_emit_compare_and_swap_exchange_loop (target, mem, val); |
7298 | if (ret) | |
7299 | return ret; | |
744accb2 AM |
7300 | |
7301 | /* If there are no other options, try atomic_test_and_set if the value | |
7302 | being stored is 1. */ | |
f8a27aa6 RH |
7303 | if (val == const1_rtx) |
7304 | ret = maybe_emit_atomic_test_and_set (target, mem, MEMMODEL_ACQUIRE); | |
744accb2 AM |
7305 | |
7306 | return ret; | |
7307 | } | |
7308 | ||
7309 | /* This function expands the atomic test_and_set operation: | |
7310 | atomically store a boolean TRUE into MEM and return the previous value. | |
7311 | ||
7312 | MEMMODEL is the memory model variant to use. | |
7313 | TARGET is an optional place to stick the return value. */ | |
7314 | ||
7315 | rtx | |
7316 | expand_atomic_test_and_set (rtx target, rtx mem, enum memmodel model) | |
7317 | { | |
7318 | enum machine_mode mode = GET_MODE (mem); | |
a6de595f | 7319 | rtx ret, trueval, subtarget; |
f8a27aa6 RH |
7320 | |
7321 | ret = maybe_emit_atomic_test_and_set (target, mem, model); | |
7322 | if (ret) | |
7323 | return ret; | |
744accb2 | 7324 | |
a6de595f RH |
7325 | /* Be binary compatible with non-default settings of trueval, and different |
7326 | cpu revisions. E.g. one revision may have atomic-test-and-set, but | |
7327 | another only has atomic-exchange. */ | |
7328 | if (targetm.atomic_test_and_set_trueval == 1) | |
7329 | { | |
7330 | trueval = const1_rtx; | |
7331 | subtarget = target ? target : gen_reg_rtx (mode); | |
7332 | } | |
7333 | else | |
7334 | { | |
7335 | trueval = gen_int_mode (targetm.atomic_test_and_set_trueval, mode); | |
7336 | subtarget = gen_reg_rtx (mode); | |
7337 | } | |
744accb2 | 7338 | |
a6de595f RH |
7339 | /* Try the atomic-exchange optab... */ |
7340 | ret = maybe_emit_atomic_exchange (subtarget, mem, trueval, model); | |
744accb2 | 7341 | |
a6de595f RH |
7342 | /* ... then an atomic-compare-and-swap loop ... */ |
7343 | if (!ret) | |
7344 | ret = maybe_emit_compare_and_swap_exchange_loop (subtarget, mem, trueval); | |
744accb2 | 7345 | |
a6de595f RH |
7346 | /* ... before trying the vaguely defined legacy lock_test_and_set. */ |
7347 | if (!ret) | |
7348 | ret = maybe_emit_sync_lock_test_and_set (subtarget, mem, trueval, model); | |
744accb2 | 7349 | |
a6de595f RH |
7350 | /* Recall that the legacy lock_test_and_set optab was allowed to do magic |
7351 | things with the value 1. Thus we try again without trueval. */ | |
7352 | if (!ret && targetm.atomic_test_and_set_trueval != 1) | |
7353 | ret = maybe_emit_sync_lock_test_and_set (subtarget, mem, const1_rtx, model); | |
7354 | ||
7355 | /* Failing all else, assume a single threaded environment and simply | |
7356 | perform the operation. */ | |
7357 | if (!ret) | |
7358 | { | |
0d03cda4 KT |
7359 | /* If the result is ignored skip the move to target. */ |
7360 | if (subtarget != const0_rtx) | |
7361 | emit_move_insn (subtarget, mem); | |
7362 | ||
a6de595f RH |
7363 | emit_move_insn (mem, trueval); |
7364 | ret = subtarget; | |
7365 | } | |
7366 | ||
7367 | /* Recall that have to return a boolean value; rectify if trueval | |
7368 | is not exactly one. */ | |
7369 | if (targetm.atomic_test_and_set_trueval != 1) | |
7370 | ret = emit_store_flag_force (target, NE, ret, const0_rtx, mode, 0, 1); | |
7371 | ||
7372 | return ret; | |
744accb2 AM |
7373 | } |
7374 | ||
7375 | /* This function expands the atomic exchange operation: | |
7376 | atomically store VAL in MEM and return the previous value in MEM. | |
7377 | ||
7378 | MEMMODEL is the memory model variant to use. | |
7379 | TARGET is an optional place to stick the return value. */ | |
7380 | ||
7381 | rtx | |
7382 | expand_atomic_exchange (rtx target, rtx mem, rtx val, enum memmodel model) | |
7383 | { | |
7384 | rtx ret; | |
7385 | ||
7386 | ret = maybe_emit_atomic_exchange (target, mem, val, model); | |
7387 | ||
7388 | /* Next try a compare-and-swap loop for the exchange. */ | |
7389 | if (!ret) | |
7390 | ret = maybe_emit_compare_and_swap_exchange_loop (target, mem, val); | |
7391 | ||
7392 | return ret; | |
7393 | } | |
7394 | ||
86951993 AM |
7395 | /* This function expands the atomic compare exchange operation: |
7396 | ||
7397 | *PTARGET_BOOL is an optional place to store the boolean success/failure. | |
7398 | *PTARGET_OVAL is an optional place to store the old value from memory. | |
7399 | Both target parameters may be NULL to indicate that we do not care about | |
7400 | that return value. Both target parameters are updated on success to | |
7401 | the actual location of the corresponding result. | |
7402 | ||
7403 | MEMMODEL is the memory model variant to use. | |
7404 | ||
7405 | The return value of the function is true for success. */ | |
7406 | ||
7407 | bool | |
7408 | expand_atomic_compare_and_swap (rtx *ptarget_bool, rtx *ptarget_oval, | |
7409 | rtx mem, rtx expected, rtx desired, | |
7410 | bool is_weak, enum memmodel succ_model, | |
7411 | enum memmodel fail_model) | |
7412 | { | |
7413 | enum machine_mode mode = GET_MODE (mem); | |
7414 | struct expand_operand ops[8]; | |
7415 | enum insn_code icode; | |
cedb4a1a RH |
7416 | rtx target_oval, target_bool = NULL_RTX; |
7417 | rtx libfunc; | |
86951993 AM |
7418 | |
7419 | /* Load expected into a register for the compare and swap. */ | |
7420 | if (MEM_P (expected)) | |
7421 | expected = copy_to_reg (expected); | |
7422 | ||
7423 | /* Make sure we always have some place to put the return oldval. | |
7424 | Further, make sure that place is distinct from the input expected, | |
7425 | just in case we need that path down below. */ | |
7426 | if (ptarget_oval == NULL | |
7427 | || (target_oval = *ptarget_oval) == NULL | |
7428 | || reg_overlap_mentioned_p (expected, target_oval)) | |
7429 | target_oval = gen_reg_rtx (mode); | |
7430 | ||
7431 | icode = direct_optab_handler (atomic_compare_and_swap_optab, mode); | |
7432 | if (icode != CODE_FOR_nothing) | |
7433 | { | |
7434 | enum machine_mode bool_mode = insn_data[icode].operand[0].mode; | |
7435 | ||
7436 | /* Make sure we always have a place for the bool operand. */ | |
7437 | if (ptarget_bool == NULL | |
7438 | || (target_bool = *ptarget_bool) == NULL | |
7439 | || GET_MODE (target_bool) != bool_mode) | |
7440 | target_bool = gen_reg_rtx (bool_mode); | |
7441 | ||
7442 | /* Emit the compare_and_swap. */ | |
7443 | create_output_operand (&ops[0], target_bool, bool_mode); | |
7444 | create_output_operand (&ops[1], target_oval, mode); | |
7445 | create_fixed_operand (&ops[2], mem); | |
464046a6 RH |
7446 | create_input_operand (&ops[3], expected, mode); |
7447 | create_input_operand (&ops[4], desired, mode); | |
86951993 AM |
7448 | create_integer_operand (&ops[5], is_weak); |
7449 | create_integer_operand (&ops[6], succ_model); | |
7450 | create_integer_operand (&ops[7], fail_model); | |
8bd7070a AK |
7451 | if (maybe_expand_insn (icode, 8, ops)) |
7452 | { | |
7453 | /* Return success/failure. */ | |
7454 | target_bool = ops[0].value; | |
7455 | target_oval = ops[1].value; | |
7456 | goto success; | |
7457 | } | |
86951993 AM |
7458 | } |
7459 | ||
7460 | /* Otherwise fall back to the original __sync_val_compare_and_swap | |
7461 | which is always seq-cst. */ | |
cedb4a1a | 7462 | icode = optab_handler (sync_compare_and_swap_optab, mode); |
86951993 AM |
7463 | if (icode != CODE_FOR_nothing) |
7464 | { | |
7465 | rtx cc_reg; | |
7466 | ||
7467 | create_output_operand (&ops[0], target_oval, mode); | |
7468 | create_fixed_operand (&ops[1], mem); | |
464046a6 RH |
7469 | create_input_operand (&ops[2], expected, mode); |
7470 | create_input_operand (&ops[3], desired, mode); | |
86951993 AM |
7471 | if (!maybe_expand_insn (icode, 4, ops)) |
7472 | return false; | |
7473 | ||
7474 | target_oval = ops[0].value; | |
86951993 AM |
7475 | |
7476 | /* If the caller isn't interested in the boolean return value, | |
7477 | skip the computation of it. */ | |
7478 | if (ptarget_bool == NULL) | |
7479 | goto success; | |
7480 | ||
7481 | /* Otherwise, work out if the compare-and-swap succeeded. */ | |
7482 | cc_reg = NULL_RTX; | |
7483 | if (have_insn_for (COMPARE, CCmode)) | |
7484 | note_stores (PATTERN (get_last_insn ()), find_cc_set, &cc_reg); | |
cedb4a1a RH |
7485 | if (cc_reg) |
7486 | { | |
7487 | target_bool = emit_store_flag_force (target_bool, EQ, cc_reg, | |
7488 | const0_rtx, VOIDmode, 0, 1); | |
7489 | goto success; | |
7490 | } | |
7491 | goto success_bool_from_val; | |
7492 | } | |
86951993 | 7493 | |
cedb4a1a RH |
7494 | /* Also check for library support for __sync_val_compare_and_swap. */ |
7495 | libfunc = optab_libfunc (sync_compare_and_swap_optab, mode); | |
7496 | if (libfunc != NULL) | |
7497 | { | |
7498 | rtx addr = convert_memory_address (ptr_mode, XEXP (mem, 0)); | |
fae67e1d | 7499 | target_oval = emit_library_call_value (libfunc, NULL_RTX, LCT_NORMAL, |
cedb4a1a RH |
7500 | mode, 3, addr, ptr_mode, |
7501 | expected, mode, desired, mode); | |
7502 | ||
7503 | /* Compute the boolean return value only if requested. */ | |
7504 | if (ptarget_bool) | |
7505 | goto success_bool_from_val; | |
7506 | else | |
7507 | goto success; | |
86951993 | 7508 | } |
cedb4a1a RH |
7509 | |
7510 | /* Failure. */ | |
86951993 AM |
7511 | return false; |
7512 | ||
cedb4a1a RH |
7513 | success_bool_from_val: |
7514 | target_bool = emit_store_flag_force (target_bool, EQ, target_oval, | |
7515 | expected, VOIDmode, 1, 1); | |
86951993 AM |
7516 | success: |
7517 | /* Make sure that the oval output winds up where the caller asked. */ | |
7518 | if (ptarget_oval) | |
7519 | *ptarget_oval = target_oval; | |
7520 | if (ptarget_bool) | |
7521 | *ptarget_bool = target_bool; | |
48ae6c13 RH |
7522 | return true; |
7523 | } | |
7524 | ||
c39169c8 RH |
7525 | /* Generate asm volatile("" : : : "memory") as the memory barrier. */ |
7526 | ||
7527 | static void | |
7528 | expand_asm_memory_barrier (void) | |
7529 | { | |
7530 | rtx asm_op, clob; | |
7531 | ||
7532 | asm_op = gen_rtx_ASM_OPERANDS (VOIDmode, empty_string, empty_string, 0, | |
7533 | rtvec_alloc (0), rtvec_alloc (0), | |
7534 | rtvec_alloc (0), UNKNOWN_LOCATION); | |
7535 | MEM_VOLATILE_P (asm_op) = 1; | |
7536 | ||
7537 | clob = gen_rtx_SCRATCH (VOIDmode); | |
7538 | clob = gen_rtx_MEM (BLKmode, clob); | |
7539 | clob = gen_rtx_CLOBBER (VOIDmode, clob); | |
7540 | ||
7541 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, asm_op, clob))); | |
7542 | } | |
7543 | ||
7544 | /* This routine will either emit the mem_thread_fence pattern or issue a | |
7545 | sync_synchronize to generate a fence for memory model MEMMODEL. */ | |
7546 | ||
7547 | #ifndef HAVE_mem_thread_fence | |
7548 | # define HAVE_mem_thread_fence 0 | |
7549 | # define gen_mem_thread_fence(x) (gcc_unreachable (), NULL_RTX) | |
7550 | #endif | |
7551 | #ifndef HAVE_memory_barrier | |
7552 | # define HAVE_memory_barrier 0 | |
7553 | # define gen_memory_barrier() (gcc_unreachable (), NULL_RTX) | |
7554 | #endif | |
7555 | ||
7556 | void | |
7557 | expand_mem_thread_fence (enum memmodel model) | |
7558 | { | |
7559 | if (HAVE_mem_thread_fence) | |
7560 | emit_insn (gen_mem_thread_fence (GEN_INT (model))); | |
88e784e6 | 7561 | else if ((model & MEMMODEL_MASK) != MEMMODEL_RELAXED) |
c39169c8 RH |
7562 | { |
7563 | if (HAVE_memory_barrier) | |
7564 | emit_insn (gen_memory_barrier ()); | |
7565 | else if (synchronize_libfunc != NULL_RTX) | |
7566 | emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode, 0); | |
7567 | else | |
7568 | expand_asm_memory_barrier (); | |
7569 | } | |
7570 | } | |
7571 | ||
7572 | /* This routine will either emit the mem_signal_fence pattern or issue a | |
7573 | sync_synchronize to generate a fence for memory model MEMMODEL. */ | |
7574 | ||
7575 | #ifndef HAVE_mem_signal_fence | |
7576 | # define HAVE_mem_signal_fence 0 | |
7577 | # define gen_mem_signal_fence(x) (gcc_unreachable (), NULL_RTX) | |
7578 | #endif | |
7579 | ||
7580 | void | |
7581 | expand_mem_signal_fence (enum memmodel model) | |
7582 | { | |
7583 | if (HAVE_mem_signal_fence) | |
7584 | emit_insn (gen_mem_signal_fence (GEN_INT (model))); | |
88e784e6 | 7585 | else if ((model & MEMMODEL_MASK) != MEMMODEL_RELAXED) |
c39169c8 RH |
7586 | { |
7587 | /* By default targets are coherent between a thread and the signal | |
7588 | handler running on the same thread. Thus this really becomes a | |
7589 | compiler barrier, in that stores must not be sunk past | |
7590 | (or raised above) a given point. */ | |
7591 | expand_asm_memory_barrier (); | |
7592 | } | |
7593 | } | |
7594 | ||
86951993 AM |
7595 | /* This function expands the atomic load operation: |
7596 | return the atomically loaded value in MEM. | |
7597 | ||
7598 | MEMMODEL is the memory model variant to use. | |
7599 | TARGET is an option place to stick the return value. */ | |
48ae6c13 RH |
7600 | |
7601 | rtx | |
86951993 | 7602 | expand_atomic_load (rtx target, rtx mem, enum memmodel model) |
48ae6c13 RH |
7603 | { |
7604 | enum machine_mode mode = GET_MODE (mem); | |
7605 | enum insn_code icode; | |
48ae6c13 | 7606 | |
86951993 AM |
7607 | /* If the target supports the load directly, great. */ |
7608 | icode = direct_optab_handler (atomic_load_optab, mode); | |
7609 | if (icode != CODE_FOR_nothing) | |
48ae6c13 | 7610 | { |
86951993 | 7611 | struct expand_operand ops[3]; |
48ae6c13 | 7612 | |
86951993 AM |
7613 | create_output_operand (&ops[0], target, mode); |
7614 | create_fixed_operand (&ops[1], mem); | |
7615 | create_integer_operand (&ops[2], model); | |
7616 | if (maybe_expand_insn (icode, 3, ops)) | |
7617 | return ops[0].value; | |
7618 | } | |
48ae6c13 | 7619 | |
86951993 AM |
7620 | /* If the size of the object is greater than word size on this target, |
7621 | then we assume that a load will not be atomic. */ | |
7622 | if (GET_MODE_PRECISION (mode) > BITS_PER_WORD) | |
7623 | { | |
7624 | /* Issue val = compare_and_swap (mem, 0, 0). | |
7625 | This may cause the occasional harmless store of 0 when the value is | |
7626 | already 0, but it seems to be OK according to the standards guys. */ | |
c51ec0a3 AM |
7627 | if (expand_atomic_compare_and_swap (NULL, &target, mem, const0_rtx, |
7628 | const0_rtx, false, model, model)) | |
7629 | return target; | |
7630 | else | |
7631 | /* Otherwise there is no atomic load, leave the library call. */ | |
7632 | return NULL_RTX; | |
48ae6c13 RH |
7633 | } |
7634 | ||
86951993 AM |
7635 | /* Otherwise assume loads are atomic, and emit the proper barriers. */ |
7636 | if (!target || target == const0_rtx) | |
7637 | target = gen_reg_rtx (mode); | |
7638 | ||
80928237 | 7639 | /* For SEQ_CST, emit a barrier before the load. */ |
88e784e6 | 7640 | if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) |
80928237 | 7641 | expand_mem_thread_fence (model); |
86951993 AM |
7642 | |
7643 | emit_move_insn (target, mem); | |
7644 | ||
80928237 RH |
7645 | /* Emit the appropriate barrier after the load. */ |
7646 | expand_mem_thread_fence (model); | |
86951993 AM |
7647 | |
7648 | return target; | |
7649 | } | |
7650 | ||
7651 | /* This function expands the atomic store operation: | |
7652 | Atomically store VAL in MEM. | |
7653 | MEMMODEL is the memory model variant to use. | |
0669295b | 7654 | USE_RELEASE is true if __sync_lock_release can be used as a fall back. |
86951993 AM |
7655 | function returns const0_rtx if a pattern was emitted. */ |
7656 | ||
7657 | rtx | |
0669295b | 7658 | expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) |
86951993 AM |
7659 | { |
7660 | enum machine_mode mode = GET_MODE (mem); | |
7661 | enum insn_code icode; | |
7662 | struct expand_operand ops[3]; | |
7663 | ||
7664 | /* If the target supports the store directly, great. */ | |
7665 | icode = direct_optab_handler (atomic_store_optab, mode); | |
48ae6c13 RH |
7666 | if (icode != CODE_FOR_nothing) |
7667 | { | |
a5c7d693 | 7668 | create_fixed_operand (&ops[0], mem); |
86951993 AM |
7669 | create_input_operand (&ops[1], val, mode); |
7670 | create_integer_operand (&ops[2], model); | |
7671 | if (maybe_expand_insn (icode, 3, ops)) | |
a5c7d693 | 7672 | return const0_rtx; |
48ae6c13 RH |
7673 | } |
7674 | ||
0669295b AM |
7675 | /* If using __sync_lock_release is a viable alternative, try it. */ |
7676 | if (use_release) | |
7677 | { | |
7678 | icode = direct_optab_handler (sync_lock_release_optab, mode); | |
7679 | if (icode != CODE_FOR_nothing) | |
7680 | { | |
7681 | create_fixed_operand (&ops[0], mem); | |
7682 | create_input_operand (&ops[1], const0_rtx, mode); | |
7683 | if (maybe_expand_insn (icode, 2, ops)) | |
7684 | { | |
7685 | /* lock_release is only a release barrier. */ | |
88e784e6 | 7686 | if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) |
c39169c8 | 7687 | expand_mem_thread_fence (model); |
0669295b AM |
7688 | return const0_rtx; |
7689 | } | |
7690 | } | |
7691 | } | |
7692 | ||
86951993 AM |
7693 | /* If the size of the object is greater than word size on this target, |
7694 | a default store will not be atomic, Try a mem_exchange and throw away | |
7695 | the result. If that doesn't work, don't do anything. */ | |
c3284718 | 7696 | if (GET_MODE_PRECISION (mode) > BITS_PER_WORD) |
48ae6c13 | 7697 | { |
744accb2 AM |
7698 | rtx target = maybe_emit_atomic_exchange (NULL_RTX, mem, val, model); |
7699 | if (!target) | |
7700 | target = maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, val); | |
86951993 AM |
7701 | if (target) |
7702 | return const0_rtx; | |
7703 | else | |
7704 | return NULL_RTX; | |
7705 | } | |
48ae6c13 | 7706 | |
80928237 | 7707 | /* Otherwise assume stores are atomic, and emit the proper barriers. */ |
5e3b173a | 7708 | expand_mem_thread_fence (model); |
48ae6c13 | 7709 | |
86951993 | 7710 | emit_move_insn (mem, val); |
48ae6c13 | 7711 | |
80928237 | 7712 | /* For SEQ_CST, also emit a barrier after the store. */ |
88e784e6 | 7713 | if ((model & MEMMODEL_MASK) == MEMMODEL_SEQ_CST) |
c39169c8 | 7714 | expand_mem_thread_fence (model); |
48ae6c13 | 7715 | |
86951993 | 7716 | return const0_rtx; |
48ae6c13 RH |
7717 | } |
7718 | ||
48ae6c13 | 7719 | |
86951993 AM |
7720 | /* Structure containing the pointers and values required to process the |
7721 | various forms of the atomic_fetch_op and atomic_op_fetch builtins. */ | |
7722 | ||
7723 | struct atomic_op_functions | |
48ae6c13 | 7724 | { |
cedb4a1a RH |
7725 | direct_optab mem_fetch_before; |
7726 | direct_optab mem_fetch_after; | |
7727 | direct_optab mem_no_result; | |
7728 | optab fetch_before; | |
7729 | optab fetch_after; | |
7730 | direct_optab no_result; | |
86951993 AM |
7731 | enum rtx_code reverse_code; |
7732 | }; | |
7733 | ||
48ae6c13 | 7734 | |
6ff336b4 AM |
7735 | /* Fill in structure pointed to by OP with the various optab entries for an |
7736 | operation of type CODE. */ | |
7737 | ||
7738 | static void | |
7739 | get_atomic_op_for_code (struct atomic_op_functions *op, enum rtx_code code) | |
7740 | { | |
7741 | gcc_assert (op!= NULL); | |
7742 | ||
7743 | /* If SWITCHABLE_TARGET is defined, then subtargets can be switched | |
7744 | in the source code during compilation, and the optab entries are not | |
7745 | computable until runtime. Fill in the values at runtime. */ | |
48ae6c13 RH |
7746 | switch (code) |
7747 | { | |
7748 | case PLUS: | |
6ff336b4 AM |
7749 | op->mem_fetch_before = atomic_fetch_add_optab; |
7750 | op->mem_fetch_after = atomic_add_fetch_optab; | |
7751 | op->mem_no_result = atomic_add_optab; | |
7752 | op->fetch_before = sync_old_add_optab; | |
7753 | op->fetch_after = sync_new_add_optab; | |
7754 | op->no_result = sync_add_optab; | |
7755 | op->reverse_code = MINUS; | |
7756 | break; | |
86951993 | 7757 | case MINUS: |
6ff336b4 AM |
7758 | op->mem_fetch_before = atomic_fetch_sub_optab; |
7759 | op->mem_fetch_after = atomic_sub_fetch_optab; | |
7760 | op->mem_no_result = atomic_sub_optab; | |
7761 | op->fetch_before = sync_old_sub_optab; | |
7762 | op->fetch_after = sync_new_sub_optab; | |
7763 | op->no_result = sync_sub_optab; | |
7764 | op->reverse_code = PLUS; | |
7765 | break; | |
48ae6c13 | 7766 | case XOR: |
6ff336b4 AM |
7767 | op->mem_fetch_before = atomic_fetch_xor_optab; |
7768 | op->mem_fetch_after = atomic_xor_fetch_optab; | |
7769 | op->mem_no_result = atomic_xor_optab; | |
7770 | op->fetch_before = sync_old_xor_optab; | |
7771 | op->fetch_after = sync_new_xor_optab; | |
7772 | op->no_result = sync_xor_optab; | |
7773 | op->reverse_code = XOR; | |
7774 | break; | |
48ae6c13 | 7775 | case AND: |
6ff336b4 AM |
7776 | op->mem_fetch_before = atomic_fetch_and_optab; |
7777 | op->mem_fetch_after = atomic_and_fetch_optab; | |
7778 | op->mem_no_result = atomic_and_optab; | |
7779 | op->fetch_before = sync_old_and_optab; | |
7780 | op->fetch_after = sync_new_and_optab; | |
7781 | op->no_result = sync_and_optab; | |
7782 | op->reverse_code = UNKNOWN; | |
7783 | break; | |
86951993 | 7784 | case IOR: |
6ff336b4 AM |
7785 | op->mem_fetch_before = atomic_fetch_or_optab; |
7786 | op->mem_fetch_after = atomic_or_fetch_optab; | |
7787 | op->mem_no_result = atomic_or_optab; | |
7788 | op->fetch_before = sync_old_ior_optab; | |
7789 | op->fetch_after = sync_new_ior_optab; | |
7790 | op->no_result = sync_ior_optab; | |
7791 | op->reverse_code = UNKNOWN; | |
7792 | break; | |
f12b785d | 7793 | case NOT: |
6ff336b4 AM |
7794 | op->mem_fetch_before = atomic_fetch_nand_optab; |
7795 | op->mem_fetch_after = atomic_nand_fetch_optab; | |
7796 | op->mem_no_result = atomic_nand_optab; | |
7797 | op->fetch_before = sync_old_nand_optab; | |
7798 | op->fetch_after = sync_new_nand_optab; | |
7799 | op->no_result = sync_nand_optab; | |
7800 | op->reverse_code = UNKNOWN; | |
7801 | break; | |
48ae6c13 RH |
7802 | default: |
7803 | gcc_unreachable (); | |
7804 | } | |
86951993 AM |
7805 | } |
7806 | ||
91f59d8b AM |
7807 | /* See if there is a more optimal way to implement the operation "*MEM CODE VAL" |
7808 | using memory order MODEL. If AFTER is true the operation needs to return | |
7809 | the value of *MEM after the operation, otherwise the previous value. | |
7810 | TARGET is an optional place to place the result. The result is unused if | |
7811 | it is const0_rtx. | |
7812 | Return the result if there is a better sequence, otherwise NULL_RTX. */ | |
7813 | ||
7814 | static rtx | |
7815 | maybe_optimize_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code, | |
7816 | enum memmodel model, bool after) | |
7817 | { | |
7818 | /* If the value is prefetched, or not used, it may be possible to replace | |
7819 | the sequence with a native exchange operation. */ | |
7820 | if (!after || target == const0_rtx) | |
7821 | { | |
7822 | /* fetch_and (&x, 0, m) can be replaced with exchange (&x, 0, m). */ | |
7823 | if (code == AND && val == const0_rtx) | |
7824 | { | |
7825 | if (target == const0_rtx) | |
7826 | target = gen_reg_rtx (GET_MODE (mem)); | |
7827 | return maybe_emit_atomic_exchange (target, mem, val, model); | |
7828 | } | |
7829 | ||
7830 | /* fetch_or (&x, -1, m) can be replaced with exchange (&x, -1, m). */ | |
7831 | if (code == IOR && val == constm1_rtx) | |
7832 | { | |
7833 | if (target == const0_rtx) | |
7834 | target = gen_reg_rtx (GET_MODE (mem)); | |
7835 | return maybe_emit_atomic_exchange (target, mem, val, model); | |
7836 | } | |
7837 | } | |
7838 | ||
7839 | return NULL_RTX; | |
7840 | } | |
7841 | ||
86951993 AM |
7842 | /* Try to emit an instruction for a specific operation varaition. |
7843 | OPTAB contains the OP functions. | |
7844 | TARGET is an optional place to return the result. const0_rtx means unused. | |
7845 | MEM is the memory location to operate on. | |
7846 | VAL is the value to use in the operation. | |
7847 | USE_MEMMODEL is TRUE if the variation with a memory model should be tried. | |
7848 | MODEL is the memory model, if used. | |
7849 | AFTER is true if the returned result is the value after the operation. */ | |
7850 | ||
7851 | static rtx | |
7852 | maybe_emit_op (const struct atomic_op_functions *optab, rtx target, rtx mem, | |
7853 | rtx val, bool use_memmodel, enum memmodel model, bool after) | |
7854 | { | |
7855 | enum machine_mode mode = GET_MODE (mem); | |
86951993 AM |
7856 | struct expand_operand ops[4]; |
7857 | enum insn_code icode; | |
7858 | int op_counter = 0; | |
7859 | int num_ops; | |
48ae6c13 | 7860 | |
86951993 AM |
7861 | /* Check to see if there is a result returned. */ |
7862 | if (target == const0_rtx) | |
48ae6c13 | 7863 | { |
86951993 AM |
7864 | if (use_memmodel) |
7865 | { | |
cedb4a1a | 7866 | icode = direct_optab_handler (optab->mem_no_result, mode); |
86951993 AM |
7867 | create_integer_operand (&ops[2], model); |
7868 | num_ops = 3; | |
7869 | } | |
7870 | else | |
7871 | { | |
cedb4a1a | 7872 | icode = direct_optab_handler (optab->no_result, mode); |
86951993 | 7873 | num_ops = 2; |
48ae6c13 RH |
7874 | } |
7875 | } | |
86951993 | 7876 | /* Otherwise, we need to generate a result. */ |
48ae6c13 RH |
7877 | else |
7878 | { | |
86951993 AM |
7879 | if (use_memmodel) |
7880 | { | |
cedb4a1a RH |
7881 | icode = direct_optab_handler (after ? optab->mem_fetch_after |
7882 | : optab->mem_fetch_before, mode); | |
86951993 | 7883 | create_integer_operand (&ops[3], model); |
cedb4a1a | 7884 | num_ops = 4; |
86951993 AM |
7885 | } |
7886 | else | |
48ae6c13 | 7887 | { |
cedb4a1a RH |
7888 | icode = optab_handler (after ? optab->fetch_after |
7889 | : optab->fetch_before, mode); | |
86951993 | 7890 | num_ops = 3; |
48ae6c13 | 7891 | } |
86951993 | 7892 | create_output_operand (&ops[op_counter++], target, mode); |
48ae6c13 | 7893 | } |
86951993 AM |
7894 | if (icode == CODE_FOR_nothing) |
7895 | return NULL_RTX; | |
7896 | ||
7897 | create_fixed_operand (&ops[op_counter++], mem); | |
7898 | /* VAL may have been promoted to a wider mode. Shrink it if so. */ | |
7899 | create_convert_operand_to (&ops[op_counter++], val, mode, true); | |
7900 | ||
7901 | if (maybe_expand_insn (icode, num_ops, ops)) | |
cedb4a1a | 7902 | return (target == const0_rtx ? const0_rtx : ops[0].value); |
86951993 AM |
7903 | |
7904 | return NULL_RTX; | |
7905 | } | |
7906 | ||
7907 | ||
7908 | /* This function expands an atomic fetch_OP or OP_fetch operation: | |
7909 | TARGET is an option place to stick the return value. const0_rtx indicates | |
7910 | the result is unused. | |
7911 | atomically fetch MEM, perform the operation with VAL and return it to MEM. | |
7912 | CODE is the operation being performed (OP) | |
7913 | MEMMODEL is the memory model variant to use. | |
7914 | AFTER is true to return the result of the operation (OP_fetch). | |
cd8b6dc5 AM |
7915 | AFTER is false to return the value before the operation (fetch_OP). |
7916 | ||
7917 | This function will *only* generate instructions if there is a direct | |
7918 | optab. No compare and swap loops or libcalls will be generated. */ | |
7919 | ||
7920 | static rtx | |
7921 | expand_atomic_fetch_op_no_fallback (rtx target, rtx mem, rtx val, | |
7922 | enum rtx_code code, enum memmodel model, | |
7923 | bool after) | |
86951993 AM |
7924 | { |
7925 | enum machine_mode mode = GET_MODE (mem); | |
6ff336b4 | 7926 | struct atomic_op_functions optab; |
86951993 AM |
7927 | rtx result; |
7928 | bool unused_result = (target == const0_rtx); | |
7929 | ||
6ff336b4 | 7930 | get_atomic_op_for_code (&optab, code); |
86951993 | 7931 | |
91f59d8b AM |
7932 | /* Check to see if there are any better instructions. */ |
7933 | result = maybe_optimize_fetch_op (target, mem, val, code, model, after); | |
7934 | if (result) | |
7935 | return result; | |
7936 | ||
86951993 AM |
7937 | /* Check for the case where the result isn't used and try those patterns. */ |
7938 | if (unused_result) | |
48ae6c13 | 7939 | { |
86951993 | 7940 | /* Try the memory model variant first. */ |
6ff336b4 | 7941 | result = maybe_emit_op (&optab, target, mem, val, true, model, true); |
86951993 AM |
7942 | if (result) |
7943 | return result; | |
48ae6c13 | 7944 | |
86951993 | 7945 | /* Next try the old style withuot a memory model. */ |
6ff336b4 | 7946 | result = maybe_emit_op (&optab, target, mem, val, false, model, true); |
86951993 AM |
7947 | if (result) |
7948 | return result; | |
f12b785d | 7949 | |
86951993 AM |
7950 | /* There is no no-result pattern, so try patterns with a result. */ |
7951 | target = NULL_RTX; | |
7952 | } | |
48ae6c13 | 7953 | |
86951993 | 7954 | /* Try the __atomic version. */ |
6ff336b4 | 7955 | result = maybe_emit_op (&optab, target, mem, val, true, model, after); |
86951993 AM |
7956 | if (result) |
7957 | return result; | |
7958 | ||
7959 | /* Try the older __sync version. */ | |
6ff336b4 | 7960 | result = maybe_emit_op (&optab, target, mem, val, false, model, after); |
86951993 AM |
7961 | if (result) |
7962 | return result; | |
7963 | ||
7964 | /* If the fetch value can be calculated from the other variation of fetch, | |
7965 | try that operation. */ | |
cedb4a1a | 7966 | if (after || unused_result || optab.reverse_code != UNKNOWN) |
86951993 AM |
7967 | { |
7968 | /* Try the __atomic version, then the older __sync version. */ | |
6ff336b4 | 7969 | result = maybe_emit_op (&optab, target, mem, val, true, model, !after); |
86951993 | 7970 | if (!result) |
6ff336b4 | 7971 | result = maybe_emit_op (&optab, target, mem, val, false, model, !after); |
86951993 AM |
7972 | |
7973 | if (result) | |
7974 | { | |
7975 | /* If the result isn't used, no need to do compensation code. */ | |
7976 | if (unused_result) | |
2b894715 | 7977 | return result; |
86951993 AM |
7978 | |
7979 | /* Issue compensation code. Fetch_after == fetch_before OP val. | |
7980 | Fetch_before == after REVERSE_OP val. */ | |
7981 | if (!after) | |
6ff336b4 | 7982 | code = optab.reverse_code; |
154b68db AM |
7983 | if (code == NOT) |
7984 | { | |
7985 | result = expand_simple_binop (mode, AND, result, val, NULL_RTX, | |
7986 | true, OPTAB_LIB_WIDEN); | |
7987 | result = expand_simple_unop (mode, NOT, result, target, true); | |
7988 | } | |
7989 | else | |
7990 | result = expand_simple_binop (mode, code, result, val, target, | |
7991 | true, OPTAB_LIB_WIDEN); | |
86951993 | 7992 | return result; |
48ae6c13 RH |
7993 | } |
7994 | } | |
7995 | ||
cd8b6dc5 AM |
7996 | /* No direct opcode can be generated. */ |
7997 | return NULL_RTX; | |
7998 | } | |
7999 | ||
8000 | ||
8001 | ||
8002 | /* This function expands an atomic fetch_OP or OP_fetch operation: | |
8003 | TARGET is an option place to stick the return value. const0_rtx indicates | |
8004 | the result is unused. | |
8005 | atomically fetch MEM, perform the operation with VAL and return it to MEM. | |
8006 | CODE is the operation being performed (OP) | |
8007 | MEMMODEL is the memory model variant to use. | |
8008 | AFTER is true to return the result of the operation (OP_fetch). | |
8009 | AFTER is false to return the value before the operation (fetch_OP). */ | |
8010 | rtx | |
8011 | expand_atomic_fetch_op (rtx target, rtx mem, rtx val, enum rtx_code code, | |
8012 | enum memmodel model, bool after) | |
8013 | { | |
8014 | enum machine_mode mode = GET_MODE (mem); | |
8015 | rtx result; | |
8016 | bool unused_result = (target == const0_rtx); | |
8017 | ||
8018 | result = expand_atomic_fetch_op_no_fallback (target, mem, val, code, model, | |
8019 | after); | |
8020 | ||
8021 | if (result) | |
8022 | return result; | |
8023 | ||
8024 | /* Add/sub can be implemented by doing the reverse operation with -(val). */ | |
8025 | if (code == PLUS || code == MINUS) | |
8026 | { | |
8027 | rtx tmp; | |
8028 | enum rtx_code reverse = (code == PLUS ? MINUS : PLUS); | |
8029 | ||
8030 | start_sequence (); | |
8031 | tmp = expand_simple_unop (mode, NEG, val, NULL_RTX, true); | |
8032 | result = expand_atomic_fetch_op_no_fallback (target, mem, tmp, reverse, | |
8033 | model, after); | |
8034 | if (result) | |
8035 | { | |
8036 | /* PLUS worked so emit the insns and return. */ | |
8037 | tmp = get_insns (); | |
8038 | end_sequence (); | |
8039 | emit_insn (tmp); | |
8040 | return result; | |
8041 | } | |
8042 | ||
8043 | /* PLUS did not work, so throw away the negation code and continue. */ | |
8044 | end_sequence (); | |
8045 | } | |
8046 | ||
cedb4a1a RH |
8047 | /* Try the __sync libcalls only if we can't do compare-and-swap inline. */ |
8048 | if (!can_compare_and_swap_p (mode, false)) | |
8049 | { | |
8050 | rtx libfunc; | |
8051 | bool fixup = false; | |
79cd6f15 | 8052 | enum rtx_code orig_code = code; |
cd8b6dc5 | 8053 | struct atomic_op_functions optab; |
cedb4a1a | 8054 | |
cd8b6dc5 | 8055 | get_atomic_op_for_code (&optab, code); |
cedb4a1a RH |
8056 | libfunc = optab_libfunc (after ? optab.fetch_after |
8057 | : optab.fetch_before, mode); | |
8058 | if (libfunc == NULL | |
8059 | && (after || unused_result || optab.reverse_code != UNKNOWN)) | |
8060 | { | |
8061 | fixup = true; | |
8062 | if (!after) | |
8063 | code = optab.reverse_code; | |
8064 | libfunc = optab_libfunc (after ? optab.fetch_before | |
8065 | : optab.fetch_after, mode); | |
8066 | } | |
8067 | if (libfunc != NULL) | |
8068 | { | |
8069 | rtx addr = convert_memory_address (ptr_mode, XEXP (mem, 0)); | |
8070 | result = emit_library_call_value (libfunc, NULL, LCT_NORMAL, mode, | |
8071 | 2, addr, ptr_mode, val, mode); | |
8072 | ||
2b894715 | 8073 | if (!unused_result && fixup) |
cedb4a1a RH |
8074 | result = expand_simple_binop (mode, code, result, val, target, |
8075 | true, OPTAB_LIB_WIDEN); | |
8076 | return result; | |
8077 | } | |
79cd6f15 HPN |
8078 | |
8079 | /* We need the original code for any further attempts. */ | |
8080 | code = orig_code; | |
cedb4a1a RH |
8081 | } |
8082 | ||
86951993 | 8083 | /* If nothing else has succeeded, default to a compare and swap loop. */ |
cedb4a1a | 8084 | if (can_compare_and_swap_p (mode, true)) |
48ae6c13 | 8085 | { |
86951993 | 8086 | rtx insn; |
48ae6c13 RH |
8087 | rtx t0 = gen_reg_rtx (mode), t1; |
8088 | ||
48ae6c13 RH |
8089 | start_sequence (); |
8090 | ||
86951993 AM |
8091 | /* If the result is used, get a register for it. */ |
8092 | if (!unused_result) | |
8093 | { | |
8094 | if (!target || !register_operand (target, mode)) | |
8095 | target = gen_reg_rtx (mode); | |
8096 | /* If fetch_before, copy the value now. */ | |
8097 | if (!after) | |
8098 | emit_move_insn (target, t0); | |
8099 | } | |
8100 | else | |
8101 | target = const0_rtx; | |
8102 | ||
f12b785d | 8103 | t1 = t0; |
48ae6c13 | 8104 | if (code == NOT) |
86951993 | 8105 | { |
23462d4d UB |
8106 | t1 = expand_simple_binop (mode, AND, t1, val, NULL_RTX, |
8107 | true, OPTAB_LIB_WIDEN); | |
8108 | t1 = expand_simple_unop (mode, code, t1, NULL_RTX, true); | |
48ae6c13 | 8109 | } |
23462d4d | 8110 | else |
86951993 AM |
8111 | t1 = expand_simple_binop (mode, code, t1, val, NULL_RTX, true, |
8112 | OPTAB_LIB_WIDEN); | |
48ae6c13 | 8113 | |
86951993 AM |
8114 | /* For after, copy the value now. */ |
8115 | if (!unused_result && after) | |
8116 | emit_move_insn (target, t1); | |
48ae6c13 RH |
8117 | insn = get_insns (); |
8118 | end_sequence (); | |
8119 | ||
8120 | if (t1 != NULL && expand_compare_and_swap_loop (mem, t0, t1, insn)) | |
86951993 | 8121 | return target; |
48ae6c13 RH |
8122 | } |
8123 | ||
8124 | return NULL_RTX; | |
8125 | } | |
2ef6ce06 RS |
8126 | \f |
8127 | /* Return true if OPERAND is suitable for operand number OPNO of | |
8128 | instruction ICODE. */ | |
8129 | ||
8130 | bool | |
8131 | insn_operand_matches (enum insn_code icode, unsigned int opno, rtx operand) | |
8132 | { | |
8133 | return (!insn_data[(int) icode].operand[opno].predicate | |
8134 | || (insn_data[(int) icode].operand[opno].predicate | |
8135 | (operand, insn_data[(int) icode].operand[opno].mode))); | |
8136 | } | |
a5c7d693 | 8137 | \f |
02972eaf RS |
8138 | /* TARGET is a target of a multiword operation that we are going to |
8139 | implement as a series of word-mode operations. Return true if | |
8140 | TARGET is suitable for this purpose. */ | |
8141 | ||
8142 | bool | |
8143 | valid_multiword_target_p (rtx target) | |
8144 | { | |
8145 | enum machine_mode mode; | |
8146 | int i; | |
8147 | ||
8148 | mode = GET_MODE (target); | |
8149 | for (i = 0; i < GET_MODE_SIZE (mode); i += UNITS_PER_WORD) | |
8150 | if (!validate_subreg (word_mode, mode, target, i)) | |
8151 | return false; | |
8152 | return true; | |
8153 | } | |
8154 | ||
4fd3a105 RS |
8155 | /* Like maybe_legitimize_operand, but do not change the code of the |
8156 | current rtx value. */ | |
8157 | ||
8158 | static bool | |
8159 | maybe_legitimize_operand_same_code (enum insn_code icode, unsigned int opno, | |
8160 | struct expand_operand *op) | |
8161 | { | |
8162 | /* See if the operand matches in its current form. */ | |
8163 | if (insn_operand_matches (icode, opno, op->value)) | |
8164 | return true; | |
8165 | ||
8166 | /* If the operand is a memory whose address has no side effects, | |
431e1124 RS |
8167 | try forcing the address into a non-virtual pseudo register. |
8168 | The check for side effects is important because copy_to_mode_reg | |
8169 | cannot handle things like auto-modified addresses. */ | |
8170 | if (insn_data[(int) icode].operand[opno].allows_mem && MEM_P (op->value)) | |
8171 | { | |
8172 | rtx addr, mem; | |
8173 | ||
8174 | mem = op->value; | |
8175 | addr = XEXP (mem, 0); | |
8176 | if (!(REG_P (addr) && REGNO (addr) > LAST_VIRTUAL_REGISTER) | |
8177 | && !side_effects_p (addr)) | |
4fd3a105 | 8178 | { |
431e1124 RS |
8179 | rtx last; |
8180 | enum machine_mode mode; | |
8181 | ||
8182 | last = get_last_insn (); | |
372d6395 | 8183 | mode = get_address_mode (mem); |
431e1124 RS |
8184 | mem = replace_equiv_address (mem, copy_to_mode_reg (mode, addr)); |
8185 | if (insn_operand_matches (icode, opno, mem)) | |
8186 | { | |
8187 | op->value = mem; | |
8188 | return true; | |
8189 | } | |
8190 | delete_insns_since (last); | |
4fd3a105 | 8191 | } |
4fd3a105 RS |
8192 | } |
8193 | ||
8194 | return false; | |
8195 | } | |
8196 | ||
a5c7d693 RS |
8197 | /* Try to make OP match operand OPNO of instruction ICODE. Return true |
8198 | on success, storing the new operand value back in OP. */ | |
8199 | ||
8200 | static bool | |
8201 | maybe_legitimize_operand (enum insn_code icode, unsigned int opno, | |
8202 | struct expand_operand *op) | |
8203 | { | |
8204 | enum machine_mode mode, imode; | |
8205 | bool old_volatile_ok, result; | |
8206 | ||
a5c7d693 | 8207 | mode = op->mode; |
a5c7d693 RS |
8208 | switch (op->type) |
8209 | { | |
8210 | case EXPAND_FIXED: | |
4fd3a105 | 8211 | old_volatile_ok = volatile_ok; |
a5c7d693 | 8212 | volatile_ok = true; |
4fd3a105 RS |
8213 | result = maybe_legitimize_operand_same_code (icode, opno, op); |
8214 | volatile_ok = old_volatile_ok; | |
8215 | return result; | |
a5c7d693 RS |
8216 | |
8217 | case EXPAND_OUTPUT: | |
8218 | gcc_assert (mode != VOIDmode); | |
4fd3a105 RS |
8219 | if (op->value |
8220 | && op->value != const0_rtx | |
8221 | && GET_MODE (op->value) == mode | |
8222 | && maybe_legitimize_operand_same_code (icode, opno, op)) | |
8223 | return true; | |
8224 | ||
8225 | op->value = gen_reg_rtx (mode); | |
a5c7d693 RS |
8226 | break; |
8227 | ||
8228 | case EXPAND_INPUT: | |
8229 | input: | |
8230 | gcc_assert (mode != VOIDmode); | |
8231 | gcc_assert (GET_MODE (op->value) == VOIDmode | |
8232 | || GET_MODE (op->value) == mode); | |
4fd3a105 RS |
8233 | if (maybe_legitimize_operand_same_code (icode, opno, op)) |
8234 | return true; | |
8235 | ||
8236 | op->value = copy_to_mode_reg (mode, op->value); | |
a5c7d693 RS |
8237 | break; |
8238 | ||
8239 | case EXPAND_CONVERT_TO: | |
8240 | gcc_assert (mode != VOIDmode); | |
8241 | op->value = convert_to_mode (mode, op->value, op->unsigned_p); | |
8242 | goto input; | |
8243 | ||
8244 | case EXPAND_CONVERT_FROM: | |
8245 | if (GET_MODE (op->value) != VOIDmode) | |
8246 | mode = GET_MODE (op->value); | |
8247 | else | |
8248 | /* The caller must tell us what mode this value has. */ | |
8249 | gcc_assert (mode != VOIDmode); | |
8250 | ||
8251 | imode = insn_data[(int) icode].operand[opno].mode; | |
8252 | if (imode != VOIDmode && imode != mode) | |
8253 | { | |
8254 | op->value = convert_modes (imode, mode, op->value, op->unsigned_p); | |
8255 | mode = imode; | |
8256 | } | |
8257 | goto input; | |
8258 | ||
8259 | case EXPAND_ADDRESS: | |
8260 | gcc_assert (mode != VOIDmode); | |
8261 | op->value = convert_memory_address (mode, op->value); | |
8262 | goto input; | |
8263 | ||
8264 | case EXPAND_INTEGER: | |
8265 | mode = insn_data[(int) icode].operand[opno].mode; | |
8266 | if (mode != VOIDmode && const_int_operand (op->value, mode)) | |
8267 | goto input; | |
8268 | break; | |
8269 | } | |
4fd3a105 | 8270 | return insn_operand_matches (icode, opno, op->value); |
a5c7d693 RS |
8271 | } |
8272 | ||
8273 | /* Make OP describe an input operand that should have the same value | |
8274 | as VALUE, after any mode conversion that the target might request. | |
8275 | TYPE is the type of VALUE. */ | |
8276 | ||
8277 | void | |
8278 | create_convert_operand_from_type (struct expand_operand *op, | |
8279 | rtx value, tree type) | |
8280 | { | |
8281 | create_convert_operand_from (op, value, TYPE_MODE (type), | |
8282 | TYPE_UNSIGNED (type)); | |
8283 | } | |
8284 | ||
8285 | /* Try to make operands [OPS, OPS + NOPS) match operands [OPNO, OPNO + NOPS) | |
8286 | of instruction ICODE. Return true on success, leaving the new operand | |
8287 | values in the OPS themselves. Emit no code on failure. */ | |
8288 | ||
8289 | bool | |
8290 | maybe_legitimize_operands (enum insn_code icode, unsigned int opno, | |
8291 | unsigned int nops, struct expand_operand *ops) | |
8292 | { | |
8293 | rtx last; | |
8294 | unsigned int i; | |
8295 | ||
8296 | last = get_last_insn (); | |
8297 | for (i = 0; i < nops; i++) | |
8298 | if (!maybe_legitimize_operand (icode, opno + i, &ops[i])) | |
8299 | { | |
8300 | delete_insns_since (last); | |
8301 | return false; | |
8302 | } | |
8303 | return true; | |
8304 | } | |
8305 | ||
8306 | /* Try to generate instruction ICODE, using operands [OPS, OPS + NOPS) | |
8307 | as its operands. Return the instruction pattern on success, | |
8308 | and emit any necessary set-up code. Return null and emit no | |
8309 | code on failure. */ | |
8310 | ||
8311 | rtx | |
8312 | maybe_gen_insn (enum insn_code icode, unsigned int nops, | |
8313 | struct expand_operand *ops) | |
8314 | { | |
f04713ee | 8315 | gcc_assert (nops == (unsigned int) insn_data[(int) icode].n_generator_args); |
a5c7d693 RS |
8316 | if (!maybe_legitimize_operands (icode, 0, nops, ops)) |
8317 | return NULL_RTX; | |
8318 | ||
8319 | switch (nops) | |
8320 | { | |
8321 | case 1: | |
8322 | return GEN_FCN (icode) (ops[0].value); | |
8323 | case 2: | |
8324 | return GEN_FCN (icode) (ops[0].value, ops[1].value); | |
8325 | case 3: | |
8326 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value); | |
8327 | case 4: | |
8328 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8329 | ops[3].value); | |
8330 | case 5: | |
8331 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8332 | ops[3].value, ops[4].value); | |
8333 | case 6: | |
8334 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8335 | ops[3].value, ops[4].value, ops[5].value); | |
86951993 AM |
8336 | case 7: |
8337 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8338 | ops[3].value, ops[4].value, ops[5].value, | |
8339 | ops[6].value); | |
8340 | case 8: | |
8341 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8342 | ops[3].value, ops[4].value, ops[5].value, | |
8343 | ops[6].value, ops[7].value); | |
82bb7d4e JH |
8344 | case 9: |
8345 | return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, | |
8346 | ops[3].value, ops[4].value, ops[5].value, | |
8347 | ops[6].value, ops[7].value, ops[8].value); | |
a5c7d693 RS |
8348 | } |
8349 | gcc_unreachable (); | |
8350 | } | |
8351 | ||
8352 | /* Try to emit instruction ICODE, using operands [OPS, OPS + NOPS) | |
8353 | as its operands. Return true on success and emit no code on failure. */ | |
8354 | ||
8355 | bool | |
8356 | maybe_expand_insn (enum insn_code icode, unsigned int nops, | |
8357 | struct expand_operand *ops) | |
8358 | { | |
8359 | rtx pat = maybe_gen_insn (icode, nops, ops); | |
8360 | if (pat) | |
8361 | { | |
8362 | emit_insn (pat); | |
8363 | return true; | |
8364 | } | |
8365 | return false; | |
8366 | } | |
8367 | ||
8368 | /* Like maybe_expand_insn, but for jumps. */ | |
8369 | ||
8370 | bool | |
8371 | maybe_expand_jump_insn (enum insn_code icode, unsigned int nops, | |
8372 | struct expand_operand *ops) | |
8373 | { | |
8374 | rtx pat = maybe_gen_insn (icode, nops, ops); | |
8375 | if (pat) | |
8376 | { | |
8377 | emit_jump_insn (pat); | |
8378 | return true; | |
8379 | } | |
8380 | return false; | |
8381 | } | |
8382 | ||
8383 | /* Emit instruction ICODE, using operands [OPS, OPS + NOPS) | |
8384 | as its operands. */ | |
8385 | ||
8386 | void | |
8387 | expand_insn (enum insn_code icode, unsigned int nops, | |
8388 | struct expand_operand *ops) | |
8389 | { | |
8390 | if (!maybe_expand_insn (icode, nops, ops)) | |
8391 | gcc_unreachable (); | |
8392 | } | |
8393 | ||
8394 | /* Like expand_insn, but for jumps. */ | |
8395 | ||
8396 | void | |
8397 | expand_jump_insn (enum insn_code icode, unsigned int nops, | |
8398 | struct expand_operand *ops) | |
8399 | { | |
8400 | if (!maybe_expand_jump_insn (icode, nops, ops)) | |
8401 | gcc_unreachable (); | |
8402 | } | |
48ae6c13 | 8403 | |
fcdd52b7 RS |
8404 | /* Reduce conditional compilation elsewhere. */ |
8405 | #ifndef HAVE_insv | |
8406 | #define HAVE_insv 0 | |
8407 | #define CODE_FOR_insv CODE_FOR_nothing | |
8408 | #endif | |
8409 | #ifndef HAVE_extv | |
8410 | #define HAVE_extv 0 | |
8411 | #define CODE_FOR_extv CODE_FOR_nothing | |
8412 | #endif | |
8413 | #ifndef HAVE_extzv | |
8414 | #define HAVE_extzv 0 | |
8415 | #define CODE_FOR_extzv CODE_FOR_nothing | |
8416 | #endif | |
8417 | ||
8418 | /* Enumerates the possible types of structure operand to an | |
8419 | extraction_insn. */ | |
8420 | enum extraction_type { ET_unaligned_mem, ET_reg }; | |
8421 | ||
8422 | /* Check whether insv, extv or extzv pattern ICODE can be used for an | |
8423 | insertion or extraction of type TYPE on a structure of mode MODE. | |
8424 | Return true if so and fill in *INSN accordingly. STRUCT_OP is the | |
8425 | operand number of the structure (the first sign_extract or zero_extract | |
8426 | operand) and FIELD_OP is the operand number of the field (the other | |
8427 | side of the set from the sign_extract or zero_extract). */ | |
8428 | ||
8429 | static bool | |
8430 | get_traditional_extraction_insn (extraction_insn *insn, | |
8431 | enum extraction_type type, | |
8432 | enum machine_mode mode, | |
8433 | enum insn_code icode, | |
8434 | int struct_op, int field_op) | |
8435 | { | |
8436 | const struct insn_data_d *data = &insn_data[icode]; | |
8437 | ||
8438 | enum machine_mode struct_mode = data->operand[struct_op].mode; | |
8439 | if (struct_mode == VOIDmode) | |
8440 | struct_mode = word_mode; | |
8441 | if (mode != struct_mode) | |
8442 | return false; | |
8443 | ||
8444 | enum machine_mode field_mode = data->operand[field_op].mode; | |
8445 | if (field_mode == VOIDmode) | |
8446 | field_mode = word_mode; | |
8447 | ||
8448 | enum machine_mode pos_mode = data->operand[struct_op + 2].mode; | |
8449 | if (pos_mode == VOIDmode) | |
8450 | pos_mode = word_mode; | |
8451 | ||
8452 | insn->icode = icode; | |
8453 | insn->field_mode = field_mode; | |
8454 | insn->struct_mode = (type == ET_unaligned_mem ? byte_mode : struct_mode); | |
8455 | insn->pos_mode = pos_mode; | |
8456 | return true; | |
8457 | } | |
8458 | ||
d2eeb2d1 RS |
8459 | /* Return true if an optab exists to perform an insertion or extraction |
8460 | of type TYPE in mode MODE. Describe the instruction in *INSN if so. | |
8461 | ||
8462 | REG_OPTAB is the optab to use for register structures and | |
8463 | MISALIGN_OPTAB is the optab to use for misaligned memory structures. | |
8464 | POS_OP is the operand number of the bit position. */ | |
8465 | ||
8466 | static bool | |
8467 | get_optab_extraction_insn (struct extraction_insn *insn, | |
8468 | enum extraction_type type, | |
8469 | enum machine_mode mode, direct_optab reg_optab, | |
8470 | direct_optab misalign_optab, int pos_op) | |
8471 | { | |
8472 | direct_optab optab = (type == ET_unaligned_mem ? misalign_optab : reg_optab); | |
8473 | enum insn_code icode = direct_optab_handler (optab, mode); | |
8474 | if (icode == CODE_FOR_nothing) | |
8475 | return false; | |
8476 | ||
8477 | const struct insn_data_d *data = &insn_data[icode]; | |
8478 | ||
8479 | insn->icode = icode; | |
8480 | insn->field_mode = mode; | |
8481 | insn->struct_mode = (type == ET_unaligned_mem ? BLKmode : mode); | |
8482 | insn->pos_mode = data->operand[pos_op].mode; | |
8483 | if (insn->pos_mode == VOIDmode) | |
8484 | insn->pos_mode = word_mode; | |
8485 | return true; | |
8486 | } | |
8487 | ||
fcdd52b7 RS |
8488 | /* Return true if an instruction exists to perform an insertion or |
8489 | extraction (PATTERN says which) of type TYPE in mode MODE. | |
8490 | Describe the instruction in *INSN if so. */ | |
8491 | ||
8492 | static bool | |
8493 | get_extraction_insn (extraction_insn *insn, | |
8494 | enum extraction_pattern pattern, | |
8495 | enum extraction_type type, | |
8496 | enum machine_mode mode) | |
8497 | { | |
8498 | switch (pattern) | |
8499 | { | |
8500 | case EP_insv: | |
8501 | if (HAVE_insv | |
8502 | && get_traditional_extraction_insn (insn, type, mode, | |
8503 | CODE_FOR_insv, 0, 3)) | |
8504 | return true; | |
d2eeb2d1 RS |
8505 | return get_optab_extraction_insn (insn, type, mode, insv_optab, |
8506 | insvmisalign_optab, 2); | |
fcdd52b7 RS |
8507 | |
8508 | case EP_extv: | |
8509 | if (HAVE_extv | |
8510 | && get_traditional_extraction_insn (insn, type, mode, | |
8511 | CODE_FOR_extv, 1, 0)) | |
8512 | return true; | |
d2eeb2d1 RS |
8513 | return get_optab_extraction_insn (insn, type, mode, extv_optab, |
8514 | extvmisalign_optab, 3); | |
fcdd52b7 RS |
8515 | |
8516 | case EP_extzv: | |
8517 | if (HAVE_extzv | |
8518 | && get_traditional_extraction_insn (insn, type, mode, | |
8519 | CODE_FOR_extzv, 1, 0)) | |
8520 | return true; | |
d2eeb2d1 RS |
8521 | return get_optab_extraction_insn (insn, type, mode, extzv_optab, |
8522 | extzvmisalign_optab, 3); | |
fcdd52b7 RS |
8523 | |
8524 | default: | |
8525 | gcc_unreachable (); | |
8526 | } | |
8527 | } | |
8528 | ||
8529 | /* Return true if an instruction exists to access a field of mode | |
8530 | FIELDMODE in a structure that has STRUCT_BITS significant bits. | |
8531 | Describe the "best" such instruction in *INSN if so. PATTERN and | |
8532 | TYPE describe the type of insertion or extraction we want to perform. | |
8533 | ||
8534 | For an insertion, the number of significant structure bits includes | |
8535 | all bits of the target. For an extraction, it need only include the | |
8536 | most significant bit of the field. Larger widths are acceptable | |
8537 | in both cases. */ | |
8538 | ||
8539 | static bool | |
8540 | get_best_extraction_insn (extraction_insn *insn, | |
8541 | enum extraction_pattern pattern, | |
8542 | enum extraction_type type, | |
8543 | unsigned HOST_WIDE_INT struct_bits, | |
8544 | enum machine_mode field_mode) | |
8545 | { | |
8546 | enum machine_mode mode = smallest_mode_for_size (struct_bits, MODE_INT); | |
8547 | while (mode != VOIDmode) | |
8548 | { | |
8549 | if (get_extraction_insn (insn, pattern, type, mode)) | |
8550 | { | |
8551 | while (mode != VOIDmode | |
8552 | && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (field_mode) | |
8553 | && !TRULY_NOOP_TRUNCATION_MODES_P (insn->field_mode, | |
8554 | field_mode)) | |
8555 | { | |
8556 | get_extraction_insn (insn, pattern, type, mode); | |
8557 | mode = GET_MODE_WIDER_MODE (mode); | |
8558 | } | |
8559 | return true; | |
8560 | } | |
8561 | mode = GET_MODE_WIDER_MODE (mode); | |
8562 | } | |
8563 | return false; | |
8564 | } | |
8565 | ||
8566 | /* Return true if an instruction exists to access a field of mode | |
8567 | FIELDMODE in a register structure that has STRUCT_BITS significant bits. | |
8568 | Describe the "best" such instruction in *INSN if so. PATTERN describes | |
8569 | the type of insertion or extraction we want to perform. | |
8570 | ||
8571 | For an insertion, the number of significant structure bits includes | |
8572 | all bits of the target. For an extraction, it need only include the | |
8573 | most significant bit of the field. Larger widths are acceptable | |
8574 | in both cases. */ | |
8575 | ||
8576 | bool | |
8577 | get_best_reg_extraction_insn (extraction_insn *insn, | |
8578 | enum extraction_pattern pattern, | |
8579 | unsigned HOST_WIDE_INT struct_bits, | |
8580 | enum machine_mode field_mode) | |
8581 | { | |
8582 | return get_best_extraction_insn (insn, pattern, ET_reg, struct_bits, | |
8583 | field_mode); | |
8584 | } | |
8585 | ||
8586 | /* Return true if an instruction exists to access a field of BITSIZE | |
8587 | bits starting BITNUM bits into a memory structure. Describe the | |
8588 | "best" such instruction in *INSN if so. PATTERN describes the type | |
8589 | of insertion or extraction we want to perform and FIELDMODE is the | |
8590 | natural mode of the extracted field. | |
8591 | ||
8592 | The instructions considered here only access bytes that overlap | |
8593 | the bitfield; they do not touch any surrounding bytes. */ | |
8594 | ||
8595 | bool | |
8596 | get_best_mem_extraction_insn (extraction_insn *insn, | |
8597 | enum extraction_pattern pattern, | |
8598 | HOST_WIDE_INT bitsize, HOST_WIDE_INT bitnum, | |
8599 | enum machine_mode field_mode) | |
8600 | { | |
8601 | unsigned HOST_WIDE_INT struct_bits = (bitnum % BITS_PER_UNIT | |
8602 | + bitsize | |
8603 | + BITS_PER_UNIT - 1); | |
8604 | struct_bits -= struct_bits % BITS_PER_UNIT; | |
8605 | return get_best_extraction_insn (insn, pattern, ET_unaligned_mem, | |
8606 | struct_bits, field_mode); | |
8607 | } | |
8608 | ||
e2500fed | 8609 | #include "gt-optabs.h" |