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3245eea0 1/* Sets (bit vectors) of hard registers, and operations on them.
23a5b65a 2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
3245eea0 3
1322177d 4This file is part of GCC
3245eea0 5
1322177d
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6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
9dcd6f09 8Software Foundation; either version 3, or (at your option) any later
1322177d 9version.
3245eea0 10
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11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
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15
16You should have received a copy of the GNU General Public License
9dcd6f09
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17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
3245eea0 19
88657302 20#ifndef GCC_HARD_REG_SET_H
b8698a0f 21#define GCC_HARD_REG_SET_H
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22
23/* Define the type of a set of hard registers. */
24
328d0797
RS
25/* HARD_REG_ELT_TYPE is a typedef of the unsigned integral type which
26 will be used for hard reg sets, either alone or in an array.
27
28 If HARD_REG_SET is a macro, its definition is HARD_REG_ELT_TYPE,
29 and it has enough bits to represent all the target machine's hard
30 registers. Otherwise, it is a typedef for a suitably sized array
31 of HARD_REG_ELT_TYPEs. HARD_REG_SET_LONGS is defined as how many.
3245eea0
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32
33 Note that lots of code assumes that the first part of a regset is
34 the same format as a HARD_REG_SET. To help make sure this is true,
99fa8911
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35 we only try the widest fast integer mode (HOST_WIDEST_FAST_INT)
36 instead of all the smaller types. This approach loses only if
2a7e31df 37 there are very few registers and then only in the few cases where
99fa8911
AP
38 we have an array of HARD_REG_SETs, so it needn't be as complex as
39 it used to be. */
328d0797 40
99fa8911 41typedef unsigned HOST_WIDEST_FAST_INT HARD_REG_ELT_TYPE;
3245eea0 42
99fa8911 43#if FIRST_PSEUDO_REGISTER <= HOST_BITS_PER_WIDEST_FAST_INT
328d0797
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44
45#define HARD_REG_SET HARD_REG_ELT_TYPE
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46
47#else
48
49#define HARD_REG_SET_LONGS \
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50 ((FIRST_PSEUDO_REGISTER + HOST_BITS_PER_WIDEST_FAST_INT - 1) \
51 / HOST_BITS_PER_WIDEST_FAST_INT)
328d0797 52typedef HARD_REG_ELT_TYPE HARD_REG_SET[HARD_REG_SET_LONGS];
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53
54#endif
55
ee3d2ecd
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56/* HARD_REG_SET wrapped into a structure, to make it possible to
57 use HARD_REG_SET even in APIs that should not include
58 hard-reg-set.h. */
59struct hard_reg_set_container
60{
61 HARD_REG_SET set;
62};
63
328d0797
RS
64/* HARD_CONST is used to cast a constant to the appropriate type
65 for use with a HARD_REG_SET. */
3245eea0 66
328d0797 67#define HARD_CONST(X) ((HARD_REG_ELT_TYPE) (X))
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68
69/* Define macros SET_HARD_REG_BIT, CLEAR_HARD_REG_BIT and TEST_HARD_REG_BIT
70 to set, clear or test one bit in a hard reg set of type HARD_REG_SET.
71 All three take two arguments: the set and the register number.
72
73 In the case where sets are arrays of longs, the first argument
74 is actually a pointer to a long.
75
76 Define two macros for initializing a set:
77 CLEAR_HARD_REG_SET and SET_HARD_REG_SET.
78 These take just one argument.
79
80 Also define macros for copying hard reg sets:
81 COPY_HARD_REG_SET and COMPL_HARD_REG_SET.
82 These take two arguments TO and FROM; they read from FROM
83 and store into TO. COMPL_HARD_REG_SET complements each bit.
84
85 Also define macros for combining hard reg sets:
86 IOR_HARD_REG_SET and AND_HARD_REG_SET.
87 These take two arguments TO and FROM; they read from FROM
88 and combine bitwise into TO. Define also two variants
89 IOR_COMPL_HARD_REG_SET and AND_COMPL_HARD_REG_SET
90 which use the complement of the set FROM.
91
56b138ae
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92 Also define:
93
94 hard_reg_set_subset_p (X, Y), which returns true if X is a subset of Y.
95 hard_reg_set_equal_p (X, Y), which returns true if X and Y are equal.
96 hard_reg_set_intersect_p (X, Y), which returns true if X and Y intersect.
97 hard_reg_set_empty_p (X), which returns true if X is empty. */
3245eea0 98
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99#define UHOST_BITS_PER_WIDE_INT ((unsigned) HOST_BITS_PER_WIDEST_FAST_INT)
100
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101#ifdef HARD_REG_SET
102
103#define SET_HARD_REG_BIT(SET, BIT) \
104 ((SET) |= HARD_CONST (1) << (BIT))
105#define CLEAR_HARD_REG_BIT(SET, BIT) \
106 ((SET) &= ~(HARD_CONST (1) << (BIT)))
107#define TEST_HARD_REG_BIT(SET, BIT) \
ae32926b 108 (!!((SET) & (HARD_CONST (1) << (BIT))))
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109
110#define CLEAR_HARD_REG_SET(TO) ((TO) = HARD_CONST (0))
328d0797 111#define SET_HARD_REG_SET(TO) ((TO) = ~ HARD_CONST (0))
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112
113#define COPY_HARD_REG_SET(TO, FROM) ((TO) = (FROM))
114#define COMPL_HARD_REG_SET(TO, FROM) ((TO) = ~(FROM))
115
116#define IOR_HARD_REG_SET(TO, FROM) ((TO) |= (FROM))
117#define IOR_COMPL_HARD_REG_SET(TO, FROM) ((TO) |= ~ (FROM))
118#define AND_HARD_REG_SET(TO, FROM) ((TO) &= (FROM))
119#define AND_COMPL_HARD_REG_SET(TO, FROM) ((TO) &= ~ (FROM))
120
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121static inline bool
122hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
123{
124 return (x & ~y) == HARD_CONST (0);
125}
126
127static inline bool
128hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
129{
130 return x == y;
131}
132
133static inline bool
134hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
135{
136 return (x & y) != HARD_CONST (0);
137}
138
139static inline bool
140hard_reg_set_empty_p (const HARD_REG_SET x)
141{
142 return x == HARD_CONST (0);
143}
328d0797 144
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145#else
146
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147#define SET_HARD_REG_BIT(SET, BIT) \
148 ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
328d0797 149 |= HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))
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CH
150
151#define CLEAR_HARD_REG_BIT(SET, BIT) \
152 ((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
328d0797 153 &= ~(HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT)))
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CH
154
155#define TEST_HARD_REG_BIT(SET, BIT) \
ae32926b
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156 (!!((SET)[(BIT) / UHOST_BITS_PER_WIDE_INT] \
157 & (HARD_CONST (1) << ((BIT) % UHOST_BITS_PER_WIDE_INT))))
3245eea0 158
99fa8911 159#if FIRST_PSEUDO_REGISTER <= 2*HOST_BITS_PER_WIDEST_FAST_INT
ea78578f 160#define CLEAR_HARD_REG_SET(TO) \
b3694847 161do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
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162 scan_tp_[0] = 0; \
163 scan_tp_[1] = 0; } while (0)
164
165#define SET_HARD_REG_SET(TO) \
b3694847 166do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
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167 scan_tp_[0] = -1; \
168 scan_tp_[1] = -1; } while (0)
169
170#define COPY_HARD_REG_SET(TO, FROM) \
b3694847 171do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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172 scan_tp_[0] = scan_fp_[0]; \
173 scan_tp_[1] = scan_fp_[1]; } while (0)
174
175#define COMPL_HARD_REG_SET(TO, FROM) \
b3694847 176do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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177 scan_tp_[0] = ~ scan_fp_[0]; \
178 scan_tp_[1] = ~ scan_fp_[1]; } while (0)
179
180#define AND_HARD_REG_SET(TO, FROM) \
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181do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
182 scan_tp_[0] &= scan_fp_[0]; \
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183 scan_tp_[1] &= scan_fp_[1]; } while (0)
184
185#define AND_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 186do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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187 scan_tp_[0] &= ~ scan_fp_[0]; \
188 scan_tp_[1] &= ~ scan_fp_[1]; } while (0)
189
190#define IOR_HARD_REG_SET(TO, FROM) \
b3694847 191do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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192 scan_tp_[0] |= scan_fp_[0]; \
193 scan_tp_[1] |= scan_fp_[1]; } while (0)
194
195#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 196do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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197 scan_tp_[0] |= ~ scan_fp_[0]; \
198 scan_tp_[1] |= ~ scan_fp_[1]; } while (0)
199
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200static inline bool
201hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
202{
203 return (x[0] & ~y[0]) == 0 && (x[1] & ~y[1]) == 0;
204}
205
206static inline bool
207hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
208{
209 return x[0] == y[0] && x[1] == y[1];
210}
211
212static inline bool
213hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
214{
215 return (x[0] & y[0]) != 0 || (x[1] & y[1]) != 0;
216}
217
218static inline bool
219hard_reg_set_empty_p (const HARD_REG_SET x)
220{
221 return x[0] == 0 && x[1] == 0;
222}
ea78578f
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223
224#else
992c944c 225#if FIRST_PSEUDO_REGISTER <= 3*HOST_BITS_PER_WIDEST_FAST_INT
ea78578f 226#define CLEAR_HARD_REG_SET(TO) \
b3694847 227do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
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228 scan_tp_[0] = 0; \
229 scan_tp_[1] = 0; \
230 scan_tp_[2] = 0; } while (0)
231
232#define SET_HARD_REG_SET(TO) \
b3694847 233do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
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234 scan_tp_[0] = -1; \
235 scan_tp_[1] = -1; \
236 scan_tp_[2] = -1; } while (0)
237
238#define COPY_HARD_REG_SET(TO, FROM) \
b3694847 239do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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240 scan_tp_[0] = scan_fp_[0]; \
241 scan_tp_[1] = scan_fp_[1]; \
242 scan_tp_[2] = scan_fp_[2]; } while (0)
243
244#define COMPL_HARD_REG_SET(TO, FROM) \
b3694847 245do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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246 scan_tp_[0] = ~ scan_fp_[0]; \
247 scan_tp_[1] = ~ scan_fp_[1]; \
248 scan_tp_[2] = ~ scan_fp_[2]; } while (0)
249
250#define AND_HARD_REG_SET(TO, FROM) \
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251do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
252 scan_tp_[0] &= scan_fp_[0]; \
253 scan_tp_[1] &= scan_fp_[1]; \
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254 scan_tp_[2] &= scan_fp_[2]; } while (0)
255
256#define AND_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 257do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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258 scan_tp_[0] &= ~ scan_fp_[0]; \
259 scan_tp_[1] &= ~ scan_fp_[1]; \
260 scan_tp_[2] &= ~ scan_fp_[2]; } while (0)
261
262#define IOR_HARD_REG_SET(TO, FROM) \
b3694847 263do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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MM
264 scan_tp_[0] |= scan_fp_[0]; \
265 scan_tp_[1] |= scan_fp_[1]; \
266 scan_tp_[2] |= scan_fp_[2]; } while (0)
267
268#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 269do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
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270 scan_tp_[0] |= ~ scan_fp_[0]; \
271 scan_tp_[1] |= ~ scan_fp_[1]; \
272 scan_tp_[2] |= ~ scan_fp_[2]; } while (0)
273
56b138ae
RS
274static inline bool
275hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
276{
277 return ((x[0] & ~y[0]) == 0
278 && (x[1] & ~y[1]) == 0
279 && (x[2] & ~y[2]) == 0);
280}
281
282static inline bool
283hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
284{
285 return x[0] == y[0] && x[1] == y[1] && x[2] == y[2];
286}
287
288static inline bool
289hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
290{
291 return ((x[0] & y[0]) != 0
292 || (x[1] & y[1]) != 0
293 || (x[2] & y[2]) != 0);
294}
295
296static inline bool
297hard_reg_set_empty_p (const HARD_REG_SET x)
298{
299 return x[0] == 0 && x[1] == 0 && x[2] == 0;
300}
ea78578f
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301
302#else
99fa8911 303#if FIRST_PSEUDO_REGISTER <= 4*HOST_BITS_PER_WIDEST_FAST_INT
ea78578f 304#define CLEAR_HARD_REG_SET(TO) \
b3694847 305do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
ea78578f
MM
306 scan_tp_[0] = 0; \
307 scan_tp_[1] = 0; \
308 scan_tp_[2] = 0; \
309 scan_tp_[3] = 0; } while (0)
310
311#define SET_HARD_REG_SET(TO) \
b3694847 312do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
ea78578f
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313 scan_tp_[0] = -1; \
314 scan_tp_[1] = -1; \
315 scan_tp_[2] = -1; \
316 scan_tp_[3] = -1; } while (0)
317
318#define COPY_HARD_REG_SET(TO, FROM) \
b3694847 319do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
ea78578f
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320 scan_tp_[0] = scan_fp_[0]; \
321 scan_tp_[1] = scan_fp_[1]; \
322 scan_tp_[2] = scan_fp_[2]; \
323 scan_tp_[3] = scan_fp_[3]; } while (0)
324
325#define COMPL_HARD_REG_SET(TO, FROM) \
b3694847 326do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
ea78578f
MM
327 scan_tp_[0] = ~ scan_fp_[0]; \
328 scan_tp_[1] = ~ scan_fp_[1]; \
329 scan_tp_[2] = ~ scan_fp_[2]; \
330 scan_tp_[3] = ~ scan_fp_[3]; } while (0)
331
332#define AND_HARD_REG_SET(TO, FROM) \
b3694847
SS
333do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
334 scan_tp_[0] &= scan_fp_[0]; \
335 scan_tp_[1] &= scan_fp_[1]; \
336 scan_tp_[2] &= scan_fp_[2]; \
ea78578f
MM
337 scan_tp_[3] &= scan_fp_[3]; } while (0)
338
339#define AND_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 340do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
ea78578f
MM
341 scan_tp_[0] &= ~ scan_fp_[0]; \
342 scan_tp_[1] &= ~ scan_fp_[1]; \
343 scan_tp_[2] &= ~ scan_fp_[2]; \
344 scan_tp_[3] &= ~ scan_fp_[3]; } while (0)
345
346#define IOR_HARD_REG_SET(TO, FROM) \
b3694847 347do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
ea78578f
MM
348 scan_tp_[0] |= scan_fp_[0]; \
349 scan_tp_[1] |= scan_fp_[1]; \
350 scan_tp_[2] |= scan_fp_[2]; \
351 scan_tp_[3] |= scan_fp_[3]; } while (0)
352
353#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
b3694847 354do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
ea78578f
MM
355 scan_tp_[0] |= ~ scan_fp_[0]; \
356 scan_tp_[1] |= ~ scan_fp_[1]; \
357 scan_tp_[2] |= ~ scan_fp_[2]; \
358 scan_tp_[3] |= ~ scan_fp_[3]; } while (0)
359
56b138ae
RS
360static inline bool
361hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
362{
363 return ((x[0] & ~y[0]) == 0
364 && (x[1] & ~y[1]) == 0
365 && (x[2] & ~y[2]) == 0
366 && (x[3] & ~y[3]) == 0);
367}
368
369static inline bool
370hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
371{
372 return x[0] == y[0] && x[1] == y[1] && x[2] == y[2] && x[3] == y[3];
373}
374
375static inline bool
376hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
377{
378 return ((x[0] & y[0]) != 0
379 || (x[1] & y[1]) != 0
380 || (x[2] & y[2]) != 0
381 || (x[3] & y[3]) != 0);
382}
383
384static inline bool
385hard_reg_set_empty_p (const HARD_REG_SET x)
386{
387 return x[0] == 0 && x[1] == 0 && x[2] == 0 && x[3] == 0;
388}
ea78578f 389
ba49cb7b 390#else /* FIRST_PSEUDO_REGISTER > 4*HOST_BITS_PER_WIDEST_FAST_INT */
ea78578f 391
3245eea0 392#define CLEAR_HARD_REG_SET(TO) \
b3694847
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393do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
394 int i; \
3245eea0
CH
395 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
396 *scan_tp_++ = 0; } while (0)
397
398#define SET_HARD_REG_SET(TO) \
b3694847
SS
399do { HARD_REG_ELT_TYPE *scan_tp_ = (TO); \
400 int i; \
3245eea0
CH
401 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
402 *scan_tp_++ = -1; } while (0)
403
404#define COPY_HARD_REG_SET(TO, FROM) \
b3694847
SS
405do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
406 int i; \
3245eea0
CH
407 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
408 *scan_tp_++ = *scan_fp_++; } while (0)
409
410#define COMPL_HARD_REG_SET(TO, FROM) \
b3694847
SS
411do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
412 int i; \
3245eea0
CH
413 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
414 *scan_tp_++ = ~ *scan_fp_++; } while (0)
415
416#define AND_HARD_REG_SET(TO, FROM) \
b3694847
SS
417do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
418 int i; \
3245eea0
CH
419 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
420 *scan_tp_++ &= *scan_fp_++; } while (0)
421
422#define AND_COMPL_HARD_REG_SET(TO, FROM) \
b3694847
SS
423do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
424 int i; \
3245eea0
CH
425 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
426 *scan_tp_++ &= ~ *scan_fp_++; } while (0)
427
428#define IOR_HARD_REG_SET(TO, FROM) \
b3694847
SS
429do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
430 int i; \
3245eea0
CH
431 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
432 *scan_tp_++ |= *scan_fp_++; } while (0)
433
434#define IOR_COMPL_HARD_REG_SET(TO, FROM) \
b3694847
SS
435do { HARD_REG_ELT_TYPE *scan_tp_ = (TO), *scan_fp_ = (FROM); \
436 int i; \
3245eea0
CH
437 for (i = 0; i < HARD_REG_SET_LONGS; i++) \
438 *scan_tp_++ |= ~ *scan_fp_++; } while (0)
439
56b138ae
RS
440static inline bool
441hard_reg_set_subset_p (const HARD_REG_SET x, const HARD_REG_SET y)
442{
443 int i;
444
445 for (i = 0; i < HARD_REG_SET_LONGS; i++)
446 if ((x[i] & ~y[i]) != 0)
447 return false;
448 return true;
449}
450
451static inline bool
452hard_reg_set_equal_p (const HARD_REG_SET x, const HARD_REG_SET y)
453{
454 int i;
455
456 for (i = 0; i < HARD_REG_SET_LONGS; i++)
457 if (x[i] != y[i])
458 return false;
459 return true;
460}
461
462static inline bool
463hard_reg_set_intersect_p (const HARD_REG_SET x, const HARD_REG_SET y)
464{
465 int i;
466
467 for (i = 0; i < HARD_REG_SET_LONGS; i++)
468 if ((x[i] & y[i]) != 0)
469 return true;
470 return false;
471}
472
473static inline bool
474hard_reg_set_empty_p (const HARD_REG_SET x)
475{
476 int i;
477
478 for (i = 0; i < HARD_REG_SET_LONGS; i++)
479 if (x[i] != 0)
480 return false;
481 return true;
482}
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483
484#endif
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485#endif
486#endif
487#endif
3245eea0 488
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489/* Iterator for hard register sets. */
490
84562394 491struct hard_reg_set_iterator
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492{
493 /* Pointer to the current element. */
494 HARD_REG_ELT_TYPE *pelt;
495
496 /* The length of the set. */
497 unsigned short length;
498
499 /* Word within the current element. */
500 unsigned short word_no;
501
502 /* Contents of the actually processed word. When finding next bit
503 it is shifted right, so that the actual bit is always the least
504 significant bit of ACTUAL. */
505 HARD_REG_ELT_TYPE bits;
84562394 506};
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507
508#define HARD_REG_ELT_BITS UHOST_BITS_PER_WIDE_INT
509
b8698a0f 510/* The implementation of the iterator functions is fully analogous to
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511 the bitmap iterators. */
512static inline void
b8698a0f 513hard_reg_set_iter_init (hard_reg_set_iterator *iter, HARD_REG_SET set,
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514 unsigned min, unsigned *regno)
515{
516#ifdef HARD_REG_SET_LONGS
517 iter->pelt = set;
518 iter->length = HARD_REG_SET_LONGS;
519#else
520 iter->pelt = &set;
521 iter->length = 1;
522#endif
523 iter->word_no = min / HARD_REG_ELT_BITS;
524 if (iter->word_no < iter->length)
525 {
526 iter->bits = iter->pelt[iter->word_no];
527 iter->bits >>= min % HARD_REG_ELT_BITS;
528
529 /* This is required for correct search of the next bit. */
530 min += !iter->bits;
531 }
532 *regno = min;
533}
534
b8698a0f 535static inline bool
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536hard_reg_set_iter_set (hard_reg_set_iterator *iter, unsigned *regno)
537{
538 while (1)
539 {
540 /* Return false when we're advanced past the end of the set. */
541 if (iter->word_no >= iter->length)
542 return false;
543
544 if (iter->bits)
545 {
546 /* Find the correct bit and return it. */
547 while (!(iter->bits & 1))
548 {
549 iter->bits >>= 1;
550 *regno += 1;
551 }
552 return (*regno < FIRST_PSEUDO_REGISTER);
553 }
b8698a0f 554
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555 /* Round to the beginning of the next word. */
556 *regno = (*regno + HARD_REG_ELT_BITS - 1);
557 *regno -= *regno % HARD_REG_ELT_BITS;
558
559 /* Find the next non-zero word. */
560 while (++iter->word_no < iter->length)
561 {
562 iter->bits = iter->pelt[iter->word_no];
563 if (iter->bits)
564 break;
565 *regno += HARD_REG_ELT_BITS;
566 }
567 }
568}
569
570static inline void
571hard_reg_set_iter_next (hard_reg_set_iterator *iter, unsigned *regno)
572{
573 iter->bits >>= 1;
574 *regno += 1;
575}
576
577#define EXECUTE_IF_SET_IN_HARD_REG_SET(SET, MIN, REGNUM, ITER) \
578 for (hard_reg_set_iter_init (&(ITER), (SET), (MIN), &(REGNUM)); \
579 hard_reg_set_iter_set (&(ITER), &(REGNUM)); \
580 hard_reg_set_iter_next (&(ITER), &(REGNUM)))
581
582
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583/* Define some standard sets of registers. */
584
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585/* Indexed by hard register number, contains 1 for registers
586 that are being used for global register decls.
587 These must be exempt from ordinary flow analysis
588 and are also considered fixed. */
589
590extern char global_regs[FIRST_PSEUDO_REGISTER];
591
6642445b 592struct target_hard_regs {
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593 /* The set of registers that actually exist on the current target. */
594 HARD_REG_SET x_accessible_reg_set;
595
596 /* The set of registers that should be considered to be register
597 operands. It is a subset of x_accessible_reg_set. */
598 HARD_REG_SET x_operand_reg_set;
599
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600 /* Indexed by hard register number, contains 1 for registers
601 that are fixed use (stack pointer, pc, frame pointer, etc.;.
602 These are the registers that cannot be used to allocate
603 a pseudo reg whose life does not cross calls. */
604 char x_fixed_regs[FIRST_PSEUDO_REGISTER];
3245eea0 605
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606 /* The same info as a HARD_REG_SET. */
607 HARD_REG_SET x_fixed_reg_set;
f5d8c9f4 608
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609 /* Indexed by hard register number, contains 1 for registers
610 that are fixed use or are clobbered by function calls.
611 These are the registers that cannot be used to allocate
612 a pseudo reg whose life crosses calls. */
613 char x_call_used_regs[FIRST_PSEUDO_REGISTER];
f5d8c9f4 614
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615 char x_call_really_used_regs[FIRST_PSEUDO_REGISTER];
616
617 /* The same info as a HARD_REG_SET. */
618 HARD_REG_SET x_call_used_reg_set;
3245eea0 619
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620 /* Contains registers that are fixed use -- i.e. in fixed_reg_set -- or
621 a function value return register or TARGET_STRUCT_VALUE_RTX or
622 STATIC_CHAIN_REGNUM. These are the registers that cannot hold quantities
623 across calls even if we are willing to save and restore them. */
624 HARD_REG_SET x_call_fixed_reg_set;
3245eea0 625
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626 /* Contains 1 for registers that are set or clobbered by calls. */
627 /* ??? Ideally, this would be just call_used_regs plus global_regs, but
628 for someone's bright idea to have call_used_regs strictly include
629 fixed_regs. Which leaves us guessing as to the set of fixed_regs
630 that are actually preserved. We know for sure that those associated
631 with the local stack frame are safe, but scant others. */
632 HARD_REG_SET x_regs_invalidated_by_call;
3245eea0 633
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634 /* Call used hard registers which can not be saved because there is no
635 insn for this. */
636 HARD_REG_SET x_no_caller_save_reg_set;
637
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638 /* Table of register numbers in the order in which to try to use them. */
639 int x_reg_alloc_order[FIRST_PSEUDO_REGISTER];
c033690d 640
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641 /* The inverse of reg_alloc_order. */
642 int x_inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
3245eea0 643
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644 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
645 HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
3245eea0 646
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647 /* For each reg class, a boolean saying whether the class contains only
648 fixed registers. */
649 bool x_class_only_fixed_regs[N_REG_CLASSES];
058e97ec 650
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651 /* For each reg class, number of regs it contains. */
652 unsigned int x_reg_class_size[N_REG_CLASSES];
058e97ec 653
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654 /* For each reg class, table listing all the classes contained in it. */
655 enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 656
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657 /* For each pair of reg classes,
658 a largest reg class contained in their union. */
659 enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 660
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661 /* For each pair of reg classes,
662 the smallest reg class that contains their union. */
663 enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
3245eea0 664
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665 /* Vector indexed by hardware reg giving its name. */
666 const char *x_reg_names[FIRST_PSEUDO_REGISTER];
667};
3245eea0 668
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669extern struct target_hard_regs default_target_hard_regs;
670#if SWITCHABLE_TARGET
671extern struct target_hard_regs *this_target_hard_regs;
672#else
673#define this_target_hard_regs (&default_target_hard_regs)
674#endif
3245eea0 675
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676#define accessible_reg_set \
677 (this_target_hard_regs->x_accessible_reg_set)
678#define operand_reg_set \
679 (this_target_hard_regs->x_operand_reg_set)
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680#define fixed_regs \
681 (this_target_hard_regs->x_fixed_regs)
682#define fixed_reg_set \
683 (this_target_hard_regs->x_fixed_reg_set)
684#define call_used_regs \
685 (this_target_hard_regs->x_call_used_regs)
686#define call_really_used_regs \
687 (this_target_hard_regs->x_call_really_used_regs)
688#define call_used_reg_set \
689 (this_target_hard_regs->x_call_used_reg_set)
690#define call_fixed_reg_set \
691 (this_target_hard_regs->x_call_fixed_reg_set)
692#define regs_invalidated_by_call \
693 (this_target_hard_regs->x_regs_invalidated_by_call)
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694#define no_caller_save_reg_set \
695 (this_target_hard_regs->x_no_caller_save_reg_set)
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696#define reg_alloc_order \
697 (this_target_hard_regs->x_reg_alloc_order)
698#define inv_reg_alloc_order \
699 (this_target_hard_regs->x_inv_reg_alloc_order)
700#define reg_class_contents \
701 (this_target_hard_regs->x_reg_class_contents)
702#define class_only_fixed_regs \
703 (this_target_hard_regs->x_class_only_fixed_regs)
704#define reg_class_size \
705 (this_target_hard_regs->x_reg_class_size)
706#define reg_class_subclasses \
707 (this_target_hard_regs->x_reg_class_subclasses)
708#define reg_class_subunion \
709 (this_target_hard_regs->x_reg_class_subunion)
710#define reg_class_superunion \
711 (this_target_hard_regs->x_reg_class_superunion)
712#define reg_names \
713 (this_target_hard_regs->x_reg_names)
96a45535 714
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715/* Vector indexed by reg class giving its name. */
716
717extern const char * reg_class_names[];
718
476c5eb6 719/* Given a hard REGN a FROM mode and a TO mode, return nonzero if
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720 REGN cannot change modes between the specified modes. */
721#define REG_CANNOT_CHANGE_MODE_P(REGN, FROM, TO) \
b0c42aed 722 CANNOT_CHANGE_MODE_CLASS (FROM, TO, REGNO_REG_CLASS (REGN))
cff9f8d5 723
88657302 724#endif /* ! GCC_HARD_REG_SET_H */
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