Created attachment 32139 [details] Bug to show the problem. The direct move support did not include support for moving long double (TFmode) and _Decimal128 (TDmode) between GPRs and VSX registers. The testcase for PR 25972 when compiled for power8 should not move registers to the stack and to the GPRs.
Note, 64-bit direct moves are fairly simple and should be implemented.
Created attachment 32142 [details] Proposed patch to fix the problem This patch adds direct move support for long double and _Decimal128 on ISA 2.07 64-bit machines.
Author: meissner Date: Sun Feb 16 03:08:03 2014 New Revision: 207808 URL: http://gcc.gnu.org/viewcvs?rev=207808&root=gcc&view=rev Log: [gcc] 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves into 64-bit and 32-bit moves. On 64-bit moves, add support for using direct move instructions on ISA 2.07. Also adjust instruction length for 64-bit. (mov<mode>_64bit, TFmode/TDmode): Likewise. (mov<mode>_32bit, TFmode/TDmode): Likewise. [gcc/testsuite] 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * gcc.target/powerpc/pr60203.c: New testsuite. Added: trunk/gcc/testsuite/gcc.target/powerpc/pr60203.c Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/rs6000.md trunk/gcc/testsuite/ChangeLog
Fixed in subversion id 207808.
Author: meissner Date: Sun Feb 16 03:19:11 2014 New Revision: 207809 URL: http://gcc.gnu.org/viewcvs?rev=207809&root=gcc&view=rev Log: [gcc] 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves into 64-bit and 32-bit moves. On 64-bit moves, add support for using direct move instructions on ISA 2.07. Also adjust instruction length for 64-bit. (mov<mode>_64bit, TFmode/TDmode): Likewise. (mov<mode>_32bit, TFmode/TDmode): Likewise. [gcc/testsuite] 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * gcc.target/powerpc/pr60203.c: New testsuite. Added: branches/ibm/gcc-4_8-branch/gcc/testsuite/gcc.target/powerpc/pr60203.c - copied unchanged from r207808, trunk/gcc/testsuite/gcc.target/powerpc/pr60203.c Modified: branches/ibm/gcc-4_8-branch/gcc/ChangeLog.ibm branches/ibm/gcc-4_8-branch/gcc/config/rs6000/rs6000.md branches/ibm/gcc-4_8-branch/gcc/testsuite/ChangeLog.ibm
Author: meissner Date: Wed Feb 19 02:14:17 2014 New Revision: 207868 URL: http://gcc.gnu.org/viewcvs?rev=207868&root=gcc&view=rev Log: 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves): Split 64-bit moves into 2 patterns. Do not allow the use of direct move for TDmode in little endian, since the decimal value has little endian bytes within a word, but the 64-bit pieces are ordered in a big endian fashion, and normal subreg's of TDmode are not allowed. (mov<mode>_64bit_dm): Likewise. (movtd_64bit_nodm): Likewise. Modified: trunk/gcc/ChangeLog trunk/gcc/config/rs6000/rs6000.md
Author: meissner Date: Wed Feb 19 02:23:10 2014 New Revision: 207869 URL: http://gcc.gnu.org/viewcvs?rev=207869&root=gcc&view=rev Log: 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves): Split 64-bit moves into 2 patterns. Do not allow the use of direct move for TDmode in little endian, since the decimal value has little endian bytes within a word, but the 64-bit pieces are ordered in a big endian fashion, and normal subreg's of TDmode are not allowed. (mov<mode>_64bit_dm): Likewise. (movtd_64bit_nodm): Likewise. Modified: branches/ibm/gcc-4_8-branch/gcc/ChangeLog.ibm branches/ibm/gcc-4_8-branch/gcc/config/rs6000/rs6000.md
Author: wschmidt Date: Fri Apr 4 15:02:38 2014 New Revision: 209111 URL: http://gcc.gnu.org/viewcvs?rev=209111&root=gcc&view=rev Log: [gcc] 2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline r207699. 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60137 * config/rs6000/rs6000.md (128-bit GPR splitter): Add a splitter for VSX/Altivec vectors that land in GPR registers. Backport from mainline r207808. 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (rreg): Add TFmode, TDmode constraints. (mov<mode>_internal, TFmode/TDmode): Split TFmode/TDmode moves into 64-bit and 32-bit moves. On 64-bit moves, add support for using direct move instructions on ISA 2.07. Also adjust instruction length for 64-bit. (mov<mode>_64bit, TFmode/TDmode): Likewise. (mov<mode>_32bit, TFmode/TDmode): Likewise. Backport from mainline r207868. 2014-02-18 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * config/rs6000/rs6000.md (mov<mode>_64bit, TF/TDmode moves): Split 64-bit moves into 2 patterns. Do not allow the use of direct move for TDmode in little endian, since the decimal value has little endian bytes within a word, but the 64-bit pieces are ordered in a big endian fashion, and normal subreg's of TDmode are not allowed. (mov<mode>_64bit_dm): Likewise. (movtd_64bit_nodm): Likewise. [gcc/testsuite] 2014-04-04 Bill Schmidt <wschmidt@linux.vnet.ibm.com> Backport from mainline r207699. 2014-02-11 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60137 * gcc.target/powerpc/pr60137.c: New file. Backport from mainline r207808. 2014-02-15 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/60203 * gcc.target/powerpc/pr60203.c: New testsuite. Added: branches/gcc-4_8-branch/gcc/testsuite/gcc.target/powerpc/pr60137.c branches/gcc-4_8-branch/gcc/testsuite/gcc.target/powerpc/pr60203.c Modified: branches/gcc-4_8-branch/gcc/ChangeLog branches/gcc-4_8-branch/gcc/config/rs6000/rs6000.md branches/gcc-4_8-branch/gcc/testsuite/ChangeLog