Bug 40842 - Poor register class choice in IRA
Summary: Poor register class choice in IRA
Status: UNCONFIRMED
Alias: None
Product: gcc
Classification: Unclassified
Component: rtl-optimization (show other bugs)
Version: 4.5.0
: P3 normal
Target Milestone: ---
Assignee: Not yet assigned to anyone
URL:
Keywords: missed-optimization, ra
Depends on:
Blocks:
 
Reported: 2009-07-23 21:31 UTC by Pat Haugen
Modified: 2022-03-08 16:20 UTC (History)
5 users (show)

See Also:
Host: powerpc64*-*-*
Target: powerpc64*-*-*
Build: powerpc64*-*-*
Known to work:
Known to fail:
Last reconfirmed:


Attachments
Testcase (2.86 KB, text/plain)
2009-07-23 21:33 UTC, Pat Haugen
Details

Note You need to log in before you can comment on or make changes to this bug.
Description Pat Haugen 2009-07-23 21:31:59 UTC
Moving this issue from bz 39976 since it is a separate problem than the original documented there.

Verified the behavior still exists using current trunk revision (150020).  The testcase comes from cpu2000 sixtrack benchmark. Following is original comment I posted:

=======
The attatched testcase exhibits the problem with the load-hit-store. It's
resulting from choosing a bad register class (GENERAL_REGS) for a pseudo that
should get assigned to FLOAT_REGS. Since there is no FPR -> GPR move for
-mcpu=power6 the copy must go through memory.  I compiled the testcase with
-m64 -O3 -mcpu=power6 using trunk revision 149376.  The pseudo in question is
361.

Following are the 3 insns referencing reg 361 in the sched1 dump (before ira):

(insn 51 238 241 8 thin6d_reduced.f:178 (set (reg:DF 361 [ prephitmp.35 ])
        (reg:DF 358 [ prephitmp.35 ])) 351 {*movdf_hardfloat64} (nil))
...
(insn 47 46 231 9 thin6d_reduced.f:178 (set (reg:DF 361 [ prephitmp.35 ])
        (reg:DF 179 [ prephitmp.35 ])) 351 {*movdf_hardfloat64} (nil))
...
(insn 196 194 198 11 thin6d_reduced.f:169 (set (mem/c/i:DF (plus:DI (reg/f:DI
477)
                (const_int 56 [0x38])) [2 crkve+0 S8 A64])
        (reg:DF 361 [ prephitmp.35 ])) 351 {*movdf_hardfloat64}
(expr_list:REG_DEAD (reg:DF 361 [ prephitmp.35 ])
        (nil)))


And from the ira dump:

Pass1 cost computation:
    a71 (r361,l1) best GENERAL_REGS, cover GENERAL_REGS
    a3 (r361,l0) best GENERAL_REGS, cover GENERAL_REGS
  a3(r361,l0) costs: BASE_REGS:0,0 GENERAL_REGS:0,0 FLOAT_REGS:0,0
LINK_REGS:156,1836 CTR_REGS:156,1836 SPECIAL_REGS:156,1836 MEM:156
  a71(r361,l1) costs: BASE_REGS:0,0 GENERAL_REGS:0,0 FLOAT_REGS:0,0
LINK_REGS:1680,1680 CTR_REGS:1680,1680 SPECIAL_REGS:1680,1680 MEM:1120


Pass 2 cost computation:
    r361: preferred GENERAL_REGS, alternative NO_REGS
  a3(r361,l0) costs: BASE_REGS:0,2240 GENERAL_REGS:0,2240 FLOAT_REGS:312,2552
LINK_REGS:234,4154 CTR_REGS:234,4154 SPECIAL_REGS:234,4154 MEM:156
  a71(r361,l1) costs: BASE_REGS:2240,2240 GENERAL_REGS:2240,2240
FLOAT_REGS:2240,2240 LINK_REGS:3920,3920 CTR_REGS:3920,3920
SPECIAL_REGS:3920,3920 MEM:3360
Comment 1 Pat Haugen 2009-07-23 21:33:24 UTC
Created attachment 18248 [details]
Testcase

The reduced testcase (since you can't attatch one when opening a new bz).