I haven't been able to reproduce this.  Please can you include the args that are being sent to cc1.

With rev173940

$ ./cc1 -fpreprocessed ice.i -quiet -O1 
ice.i: In function 'bar':
ice.i:33:1: internal compiler error: in get_arm_condition_code, at config/arm/arm.c:17021
Please submit a full bug report,
with preprocessed source if appropriate.
See <http://gcc.gnu.org/bugs.html> for instructions.

I was hoping the compiler command would tell me what -mcpu it was defaulting to.

Anyway, I have managed to reproduce it now, by compiling as follows:

  cc1 -fpreprocessed 49030.i -quiet -O1 -o 49030.s -mcpu=arm7tdmi -marm

Note that it all works with -mthumb and/or -mcpu=cortex-a9.

I have tried this with my old toolchain and it is broken as far back as r164700.

(In reply to comment #3)
> I was hoping the compiler command would tell me what -mcpu it was defaulting
> to.

I'm using an arm-unknown-linux-gnueabi configuration which defaults an arm10tdmi.

linux-eabi.h:#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm10tdmi

The same assert is seen in https://bugs.launchpad.net/ubuntu/+source/gcc-4.5/+bug/689887 in Thumb-2 mode on trunk r174795.

Chung-Lin posted a patch at http://gcc.gnu.org/ml/gcc-patches/2011-03/msg00790.html but there are bootstrap issues.

Adding -fno-if-conversion works around the problem.

It's caused by r161764:

Author: sandra
Date: Sat Jul  3 01:00:37 2010
New Revision: 161764

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=161764
Log:
2010-07-02  Daniel Jacobowitz  <dan@codesourcery.com>
	    Julian Brown  <julian@codesourcery.com>
	    Sandra Loosemore <sandra@codesourcery.com>

	gcc/
	* config/arm/arm.c (arm_canonicalize_comparison): Canonicalize DImode
	comparisons.  Adjust to take both operands.
	(arm_select_cc_mode): Handle DImode comparisons.
	(arm_gen_compare_reg): Generate a scratch register for DImode
	comparisons which require one.  Use xor for Thumb equality checks.
	(arm_const_double_by_immediates): New.
	(arm_print_operand): Allow 'Q' and 'R' for constants.
	(get_arm_condition_code): Handle new CC_CZmode and CC_NCVmode.
        ...

Created attachment 24503 [details]
more reduced test case, ICEs at -O1 for armv5te and armv6

Using this slightly more reduced test case I've found that gcc transforms

(set (reg:CC_NCV ...) (compare:CC_NCV (reg:DI ...) (const_int 1 ...)))
(if_then_else (ge (reg:CC_NCV ...) ...) ...)

to

(set (reg:CC_NCV ...) (compare:CC_NCV (reg:DI ...) (const_int 0 ...)))
(if_then_else (gt (reg:CC_NCV ...) ...)

because ifcvt calls noce_get_condition which calls canonicalize_condition, and the latter has a general rule to transform (GE x const) to (GT x const-1).

So the careful code in e.g. cbranchdi4 to not generate unimplemented comparisons is neutralized by generic code.

Do DImode comparisons really have to be asymmetric? I.e., could CC_NCV be removed?  I see that LT is apparently supported so why can't GT be too?

I have a preliminary patch which creates a clone of *arm_cmpdi_insn that does a reverse comparison, via a new CC mode for must-be-reversed comparisons, and corresponding updates to arm_select_cc_mode and get_arm_condition_code.  It's the same transformation from eg (GT x y) to (LT y x) that cstoredi4 does, only later so it can handle problematic comparisons introduced by the middle-end.

This fixes the ICEs on the two test cases in this PR.  I'll do a full bootstrap and regtest as soon as my test machine is done with its current bootstrap and regtest cycle.

I'll send the FSF Yet Another Ping about my employer's copyright disclaimer first thing tomorrow.  They've had the papers since January or February...

Author: rsandifo
Date: Wed Sep  7 13:48:03 2011
New Revision: 178636

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=178636
Log:
gcc/
	PR target/49030
	* config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
	* config/arm/arm.c (maybe_get_arm_condition_code): New function,
	reusing the old code from get_arm_condition_code.  Return ARM_NV
	for invalid comparison codes.
	(get_arm_condition_code): Redefine in terms of
	maybe_get_arm_condition_code.
	* config/arm/predicates.md (arm_comparison_operator): Use
	maybe_get_arm_condition_code.

gcc/testsuite/
	PR target/49030
	* gcc.dg/torture/pr49030.c: New test.

Added:
    trunk/gcc/testsuite/gcc.dg/torture/pr49030.c
Modified:
    trunk/gcc/ChangeLog
    trunk/gcc/config/arm/arm-protos.h
    trunk/gcc/config/arm/arm.c
    trunk/gcc/config/arm/predicates.md
    trunk/gcc/testsuite/ChangeLog

I am out of the office until September 19th. For emergencies please contact Fred Plante.

Author: gjl
Date: Fri Sep  9 17:00:26 2011
New Revision: 178736

URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=178736
Log:
	PR target/49030
	* gcc.dg/torture/pr49030.c: Run only if target int32plus.


Modified:
    trunk/gcc/testsuite/ChangeLog
    trunk/gcc/testsuite/gcc.dg/torture/pr49030.c

Fixed on trunk, and not marked as a regression.